Distributed System Interface (DSI) Sensor Interface

www.DataSheet4U.com Freescale Semiconductor Technical Data Document Number: MC33793 Rev 13.0, 11/2006 Distributed System Interface (DSI) Sensor Interface The 33793 is a slave Distributed System Interface (DSI) device that is optimized as a sensor interface. The device contains circuits to power sensors such as accelerometers and to digitize the analog level from the sensor. The device is controlled by commands over the DSI bus and returns measured data over the bus. Features • Conforms to DSI Specification Version 1 • 4-Channel, 8-Bit Analog-to-Digital Converter (ADC) • 4 Pins Configurable as Analog or Logic Inputs or as Logic Outputs • Provides Regulated +5.0 V Output for Sensor Power from Bus • Additional High-Drive Logic Output • Undervoltage Fault Detection and Signaling • On-Board Clock (No External Elements Required) • Field-Programmable Address • Default and Field-Programmable as a DSI Daisy Chain Device • Recognizes Reverse Initialization for Open Bus Fault Tolerance • Detects Short to Battery on Bus Switch and Prevents Its Closure • Pb-Free Packaging Designated by Suffix Code EF 33793/A DISTRIBUTED SYSTEM INTERFACE SCALE 2:1 D SUFFIX EF SUFFIX (Pb-FREE) 98ASB42566B 16-PIN SOICN ORDERING INFORMATION Device MC33793D/R2 MCZ33793EF/R2 MCZ33793AEF/R2 -40°C to 150°C 16 SOICN Temperature Range (TJ) Package 33790 GND DSIO X-Y Accelerometer Error Test X Y GND VCC 33793 BUSIN BUSRTN I/O0 I/O1 I/O2 I/O3 BUSOUT H_Cap REGOUT LOGOUT AGND Multiple DSI Slaves 33793 BusIN Figure 1. 33793 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006. All rights reserved. DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Freescale Part No. MCZ33793EF/R2 MCZ33793AEF/R2 Other Significant Device Variations Existing capacity Capacity expansion 33793 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM HCAP Rectifiers BUSIN Bus Switch 0 – 35 V Bi-Directional Forward Receiver Data Response Current 0 –11 mA 7.0 mA/µS Received Message from MCU Oscillator 4.0 MHz DataOut <3:0> BUSOUT Reverse Receiver Data Frame Frame BUSRTN Bandgap Reference Bandgap Reference Bus Return Logic Command Decode State Machine Response Generation 4 LOGOUT Power Management 5.0 V Regulator BG Reference Bias Currents Supply Comparators POR Logic Out High Current Buffer I/O Buffers DataOut <0> IO0 IO1 IO2 IO3 DataOut <1> Address A<3:0> 4 Bits NVM DataOut <2> I/O0 I/O1 I/O2 I/O<3:0> I/O3 GND SEL DataOut <3> 4:1 MUX ADC 8 Bits Undervoltage Detector BG Figure 2. 33793 Simplified Internal Block Diagram 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS BUSRTN I/O0 AGND I/O1 AGND I/O3 NC I/O2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BUSOUT NC BUSIN NC H_CAP REGOUT NC LOGOUT Figure 3. 33793 Pin Connections Table 2. 33793 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. Pin Number 1 2 3, 5 4 6 7, 10, 13, 15 8 Pin Name BUSRTN I/O0 AGND I/O1 I/O3 NC I/O2 Pin Function Power Input/Output Ground Input/Output Input/Output No Connect Input/Output Formal Name Bus Return Logic I/O Analog Ground Logic I/O Logic I/O No Connect Logic I/O Definition This pin provides the common return for power and signalling. This pin can be used to provide a logic level output, a logic input, or an analog-to-digital (A/D) input. This pin is the low reference level and power return for the analog-todigital converter (ADC). This pin can be used to provide a logic level output, a logic input, or an A/D input. This pin can be used to provide a logic level output, a logic input, or an A/D input. These pins have no internal connections. This pin can be used to provide a logic level output, a logic input, or an A/D input. This is a logic output with higher pull-up drive capability than the standard logic I/O. This pin provides a regulated 5.0 V output. The power is derived from the bus. A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods. This pin attaches to the bus and responds to initialization commands. This pin attaches to the bus and responds to reverse initialization commands. 9 11 12 LOGOUT REGOUT H_CAP Output Output Output Logic Out Regulator Output Holding Capacitor 14 16 BUSIN BUSOUT Input Output DSI Bus Input DSI Bus Output 33793 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS I/O Pin Voltage I/O Pin Current BUSIN, BUSOUT, BUSRTN, and H_CAP Voltage BUSIN, BUSOUT, BUSRTN, and H_CAP Current (Continuous) ESD Protection (1) Symbol Value Unit VIO IIO VIN IIN VESD1 VESD2 -0.3 to VREGOUT + 0.5 5.0 -0.3 to 40 250 ±2000 ±200 V mA V mA V Human Body Model Machine Model THERMAL RATINGS Storage Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow Thermal Resistance Junction to Case (2) (3) TSTG TJ , TPPRT RθJC -55 to 150 -40 to 150 Note 3. 150 °C °C °C °C/W Notes 1. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V < VH_CAP < 30 V, -40°C < TA < 85°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Internal Quiescent Current Drain VH_CAP = 25 V, Logout = 0, I/O = Input BUSIN or BUSOUT to H_CAP Rectifier Voltage Drop IBUSIN or IBUSOUT = 15 mA IBUSIN or IBUSOUT = 100 mA BUSIN + BUSOUT Bias Current VBUSIN or VBUSOUT = 8.0 V, VH_CAP = 9.0 V VBUSIN or VBUSOUT = 0.5 V, VH_CAP = 25 V Rectifier Leakage Current VBUSIN or VBUSOUT = 5.0 V, VH_CAP = 25 V Reg0ut 5.5 V > VH_CAP > 25 V, IRO = 12 mA RegOut Line Regulation IRO = 12 mA, 5.5 V > VH_CAP > 25 V RegOut Load Regulation IRO = 0 to 12 mA, 5.5 V > VH_CAP > 25 V Undervoltage Lockout Proportional to unloaded VREGOUT Bus Switch Resistance VBI = 8.0 V, IBO = -80 mA (Bus Switch Active) I/O0 and I/O3 Pull-Down Current 0 < VBUSIN or VBUSOUT < 1.0 V I/O1 and I/O2 Pull-Up Current VRO < VBUSIN or VBUSOUT < VRO - 1.0 V BUSIN and BUSOUT Logic Thresholds Low High Logic Duty Cycle (assured by design) Logic 0 Logic 1 BUSIN + BUSOUT Response Current VBUSIN and/or VBUSOUT = 4.0 V ADC Code Conversion Error (INL) ADC Full-scale Error I/O Logic Input Thresholds Logic High Logic Low VIH VIL 0.7 – 0.54 0.51 – 0.3 ADCINL ADCFS DCL DCH IRSP 9.9 – – 11 – – 12.1 < 1.0 3 LSB counts VRO 10 60 33 67 40 90 mA VTHL VTHH 2.8 5.5 3.0 6.0 3.2 6.5 % IPU -7.0 -11 -13 V IPD 7.0 11 13 µA RSW – 4.0 8.0 µA VUVL 0.93 0.95 0.97 Ω VRLD – 2.3 100 VRO VRLINE – 71 180 mV VREG 4.75 5.0 5.25 mV IRLKG -20 – 100 V IBIAS -100 – – – 100 20 µA VRECT – – 0.75 0.9 1.0 1.2 µA Symbol IQ – – 3.0 V Min Typ Max Unit mA 33793 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V < VH_CAP < 30 V, -40°C < TA < 85°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic I/O Logic Output Levels Output Low (IL = 1.0 mA) Output High (IL = -500 µA) LOGOUT Output Levels Output Low (IL = 500 µA) Output High (IL = -10 mA, 6.2 V < VH_CAP < 25 V) Output High (IL = -100 µA, 6.2 V < VH_CAP < 25 V) Programming Time From Positive Edge of BUSIN or BUSOUT > VTHH on Program Command to Following Command Negative Transition < VTHH NVM BUSIN or BUSOUT Programming Voltage NVMVP VLOL VLOH1 VLOH2 TPROG 100 22.25 200 – 1000 30 V 0 4.7 – 0.2 5.0 – 0.5 5.3 VRO+0.5 ms VOL VOH 0 0.8 0.08 0.985 0.5 1.0 V VRO V Symbol Min Typ Max Unit 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions -0.3 V ≤ VBUSIN or VBUSOUT ≤ 30 V, 5.5 V ≤ VH_CAP ≤ 30 V, -40°C ≤ TA ≤ 85°C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Initialization to Bus Switch Closing Loss of Signal Reset Time Maximum Time Below Frame Threshold ADC Code Conversion Time (Go, No-Go Test) BUSIN and BUSOUT Res