Two-Channel Distributed System Interface (DSI) Physical Interface Device

www.DataSheet4U.com Freescale Semiconductor Advance Information Document Number: MC33790 Rev 10.0, 12/2006 Two-Channel Distributed System Interface (DSI) Physical Interface Device The 33790 is a dual channel physical layer interface IC for the Distributed System Interface (DSI) bus. It is designed to meet automotive requirements. It can also be used in non automotive applications. It supports bidirectional communication between slave and master ICs. Some slave devices derive a regulated 5.0 V from the bus, which can be used to power sensors, thereby eliminating the need for additional circuitry and wiring. Features • • • • • • • • • • Two Independent DSI Compatible Buses Pinout Matched to MC68HC55 (SPI to DSI Logic) Wave-Shaped Bus Output Voltage Independent Thermal Shutdown and Current Limit Return Signalling Current Detection Internal Logic Input Pull ups and Pull downs On-Board Charge Pump 2.0 kV ESD Capability Communications Rate Up to 150 kbps Pb-Free Packaging Designated by Suffix Code EG Device MC33790DW / R2 MCZ33790EG / R2 33790 DISTRIBUTED SYSTEM INTERFACE (DSI) DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42567B 16-PIN SOICW ORDERING INFORMATION Temperature Range (TA) -40°C to 85°C Package 16 SOICW MC68HC55 DSI0F DSI0S Protocol Converter DSI0R DSI1F DSI1S DSI1R CPCAP 33790 VDD GND DSI0O VSUP DSI1O GND +5.0 V +25 V 33793 MCU DSI SLAVE DEVICE BUS_IN BUS_OUT 33793 BUS_IN BUS_OUT 33793 Figure 1. 33790 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VDD (+5.0 V) CPCAP VSUP (IDLE Level) + Internal Bias Charge Pump Bus Supply Voltage DSI0F DSI0S WaveShaper Transmitter Driver Bus Current Sense DSI0O DSI Bus DSI0R GND + DSI1F DSI1S WaveShaper Transmitter Driver Bus Current Sense DSI1O DSI Bus DSI1R Figure 2. 33790 Simplified Internal Block Diagram 33790 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R NC CPCAP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD GND DSI0O VSUP DSI10 GND NC NC Figure 3. 33790 Pin Connections Table 1. 33790 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 8. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name DSI0F DSI0S DSI0R DSI1F DSI1S DSI1R NC CPCAP NC NC GND DSI1O VSUP DSI0O GND VDD Definition This logic input controls the frame output for DSI channel 0 in accordance with Table 5, page 8. This logic input controls the signalling output for DSI channel 0 in accordance with Table 5, page 8. This logic output provides the return data for DSI channel 0 in accordance with Table 5, page 8. This logic input controls the frame output for DSI channel 1 in accordance with Table 5, page 8. This logic input controls the signalling output for DSI channel 1 in accordance with Table 5, page 8. This logic output provides the return data for DSI channel 1 in accordance with Table 5, page 8. Unused. Used to store and filter charge pump output. Unused. Unused. Circuit and bus ground return. DSI bus 1 input / output. Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus. DSI bus 0 input / output. Circuit and bus ground return. 5.0 V logic supply input. 33790 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Supply Voltage Continuous Load Dump - t < 300 ms Maximum Voltage on Input / Output Pins VSUP VSUP (t) VDD DSIxS, DSIxF DSIxO (1) Storage Temperature Operating Ambient Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow (2), (3) Continuous Current per Pin TSTG TA TJ TPPRT VDD DSIxR VSUP Thermal Resistance Junction to Ambient Thermal Shutdown ESD Voltage (All Pins) (4) Human Body Model Machine Model VESD1 VESD2 ± 2000 ± 200 RθJA TSD (1) Symbol Value Unit V - 0.5 to 25 40 - 0.3 to 5.5 - 0.3 to VDD + 0.3 - 0.3 to VSUP + 0.3 - 55 to 150 -40 to 85 - 40 to 150 Note 3 0 to 10 - 2.5 to 5.0 500 45 155 to 190 °C / W °C V °C °C °C °C mA V Notes 1. R = 0 Ω. 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 4. ESD1 performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500 Ω), ESD2 performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 33790 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Characteristic SUPPLY ISUP Supply Current / Channel (Not Including IOUT) DSIx0 = Idle Voltage, -100 mA ≤ IOUT ≤ 0 mA DSIx0 = Output High Voltage, IOUT = 12 mA IDD Supply Current / Channel BUS TRANSMITTER VSUP to DSIxO ON Resistance (During Idle) IOUT = -100 mA Output High Voltage DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA) Output Low Voltage DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA) Output High-Side Current Limit (5) Output Low-Side Current Limit (5) Input Leakage DSIxO When DSIxF Is High and DSIxS Is Low (0 V ≤ DSIxO ≤ Min (VSUP = 16.5 V)) BUS RECEIVER Return Current Threshold MICROCONTROLLER INTERFACE Logic Input Thresholds DSIxS, DSIxF Output High Voltage DSIxR Pin = -0.5 mA Output Low Voltage DSIxR Pin = 1.0 mA Internal Pullup for DSIxF Internal Pulldown for DSIxS Notes 5. After 10 µs settling time (assured by design). IIL IIH VOL 0.0 -100 10 – – – 0.2 VDD -10 100 µA µA VIN(TH) VOH 0.8 VDD – VDD V 1.10 – 2.20 V V IRH - 5.0 - 6.0 - 7.0 mA ICLH ICLL DSIIB - 200 – 50 DSIVOL 1.325 - 100 110 1.5 – – 1.675 -200 220 mA mA µA DSIVOH 4.175 4.5 4.825 V RDS(ON) – – 10 V Ω ISUPI ISUPH IDD – – – 1.35 5.0 0.5 3.25 9.00 1.0 mA mA Symbol Min Typ Max Unit 33790 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Characteristic MICROCONTROLLER INTERFACE Microcontroller Signal Cycle Time Microcontroller Signal Low Time Microcontroller Signal High Time Microcontroller Signal Duty Cycle for Logic Zero Microcontroller Signal Duty Cycle for Logic One Microcontroller Signal Slew Time Frame Start to Signal Delay Time Signal End to Frame End Delay Time Rise Time (6) Fall Time (6) BUS TRANSMITTER Idle to Frame and Frame to Idle Slew Rate C ≤ 5.0 nF Signal High to Low and Signal Low to High Slew Rate C ≤ 5.0 nF Data Valid (VSUPx = 25 V, CL ≤ 5.0 nF) DSIxF, VIN(TH) to DSIxO = 5.3 V DSIxS, VIN(TH) to DSIxO = 2.6 V DSIxS, VIN(TH) to DSIxO = 3.4 V DSIxF, VIN(TH) to DSIxO = 7.0 V BUS RECEIVER Receiver Delay Time tDRH: I = IRH to DSIxR = 2.5 V tDRL: I = IRH to DSIxR = 2.5 V t DRH t DRL – – 400 400 750 750 ns t DVLD1 t DVLD2 tDVLD3 tDVLD4 2.44 0.25 0.25 0.25 – – – – 6.56 1.3 1.3 1.3 t SLEW (SIGNAL) 3.0 4.5 8.0 µs t SLEW (FRAME) 3.0 6.0 10.0 V/µs V/µs (6) Symbol Min Typ Max Unit t CYC t CYCL t CYCH DCLO DCHI t SLEW t DLY1 t DLY2 t RISE t FALL 6.6 2.0 2.0 30 60.0 – t cyc - 0.1 1.0 0 0 – – – 33 66.7 – t cyc – – – 1000 667 667 36 72.0 500 t cyc + 0.1 – 100 100 µs µs µs % % ns µs µs ns ns Notes 6. Slew times and rise and fall times between 10% and 90% of output high and low levels. 33790 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING CHARACTERISTICS TIMING CHARACTERISTICS tCYC tCYCH 5.0 V tCYC tDLY2 DSIxS VIN(TH) 0V tCYCL tDLY1 5.0 V tRISE tFALL tRISE DSIxF VIN(TH) 0V 25 V 7.0 V tDVLD1 tDVLD3 tDVLD2 Note (7) tSLEW(FRAME) tSLEW(SIGNAL) tDVLD4 DSIxO 5.0 V DSIVOH 4.5 V 3.0 V 1.5 V tTAT IOUT IRH 0 mA (Note (8)) tDRH 5.0 V tDRL (Note (9)) DSIxR 0V Figure 4. Timing Characteristics Notes 7. Typical BUSIN / BUSOUT logic thresholds (VTHL) from MC33793 datasheet. 8. 9. tTAT (Turnaround Time) is dependent upon wire length, bus loads, and slave response characteristics. DSIxR stable on falling edge of DSIxS or rising edge of DSIxF. 33790 Analog Integrated Circuit Device Data Freescale Semiconductor 7 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33790 is designed to provide the interface between logic and the DSI bus. It accepts signals with a typical 0 V to 5.0 V logic level to control the state of the bus output (Idle Level, Logic High Level, Logic Low Level, and High Impedance). It detects the current drawn from the bus output during signaling and outputs a 0 V to 5.0 V logic level corresponding to the bus current being above (Logic [1] out) the bus return logic [1] current or below (Logic [0] out). The 33790 contains current limiting of the bus outputs as required by the DSI Bus specification and thermal shutdown to protect itself from