System Basis Chip

www.DataSheet4U.com Freescale Semiconductor Advance Information Document Number: MC33742 Rev. 10.0, 5/2007 System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver The 33742 and the 33742S are SPI-controlled System Basis Chips (SBCs) combining many frequently used functions along with a CAN 2.0compliant transceiver, used in many automotive electronic control units (ECUs). The 33742 SBC has a fully protected fixed 5.0 V low dropout internal regulator with current limiting, overtemperature pre-warning, and reset. A second 5.0 V regulator can be implemented using external pass PNP bipolar junction pass transistor driven by the SBC’s external V2 sense input and V2 output drive pins. The SBC has four main operating modes: Normal, Standby, Stop, and Sleep mode. Additionally there is an internally switched high-side power supply output, four wake-up inputs pins, a programmable window watchdog, interrupt, reset, and a SPI module for communication and control. The high-speed CAN A and B transceiver is available for intermodule communication. Features • 1.0 Mbps CAN Transceiver Bus Interface with Bus Diagnostic Capability • SPI Control at Frequencies up to 4.0 Mhz • 5.0 V Low Dropout Voltage Regulator with Current Limiting, Overtemperature Pre-Warning, and Output Monitoring and Reset • A Second 5.0 V Regulator Capability using an External Series Pass Transistor • Normal, Standby, Stop, and Sleep Modes of Operation with Low Sleep and Stop Mode Current • A High-Side (HS) Switch Output Driver for Controlling External Circuitry. • Pb-Free Packaging Designated by Suffix Code EG and EP 33742 33742S SYSTEM BASIS CHIP DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW EP SUFFIX (PB-FREE) 98ARH99048A 48-PIN QFN ORDERING INFORMATION Device MC33742DW/R2 MCZ33742EG/R2 MC33742SDW/R2 MCZ33742SEG/R2 PCZ33742EP/R2 48 QFN - 40°C to 125°C 28 SOICW Temperature Range (TA) Package VPWR 33742 5.0 V VDD VSUP V2CTRL V2 L0 L1 L2 L3 WDOG HS CANH CANL GND V2 MCU CS SCLK MOSI MISO RST CS SCLK MOSI MISO INT TXD RXD VPWR SPI Safe Circuitry ECU Local Supply Twisted Pair CAN Bus GND Figure 1. 33742 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Differences During a Reset Condition Part No. 33742 Reset Duration 15 ms (typical) Device Differences The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up and a VDD undervoltage condition is detected and the watchdog register is not properly triggered. The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up and a VDD undervoltage condition is detected and the watchdog register is not properly triggered. See Page page 19 33742S 3.5 ms (typical) page 19 33742 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM V2CTRL V2 VSUP VSUP Monitor Dual Voltage Regulator V1 Monitor 5.0 V / 200 mA V1 HS Control Mode Control Oscillator HS Interrupt Watchdog Reset INT WDOG RST MOSI SCLK MISO CS L1 L2 L3 L4 Programmable Wake-Up Input SPI CANH CANL High-Speed 1.0 Mbps CAN Physical Interface TXD RXD GND Figure 2. 33742 Simplified Internal Block Diagram 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS RXD TXD VDD RST INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 WDOG CS GND GND GND GND V2 V2CTRL VSUP HS L0 MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 Figure 3. 33742 28-Pin Connections Table 2. 33742 28-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 22. Pin 1 2 3 4 5 6–9 20 – 23 10 11 12 13 14 –17 18 19 24 25 26 27 28 Pin Name RXD TXD VDD RST INT GND V2 V2CTRL VSUP HS L0- L3 CANH CANL SCLK MISO MOSI CS WDOG Formal Name Receive Data Transmit Data Voltage Digital Drain Reset Output (Active LOW) Interrupt Output (Active LOW) Ground Voltage Source 2 Voltage Source 2 Control Voltage Supply High-Side Output Level 0 - 3 Inputs CAN High Output CAN Low Output Serial Data Clock Master In Slave Out Master Out Slave In Chip Select (Active LOW) Watchdog Output (Active LOW) CAN bus receive data output pin. CAN bus transmit data input pin. Definition 5.0 V regulator output pin. Supply pin for the MCU. This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. These device ground pins are internally connected to the package lead frame to provide a 33742-to-PCB thermal path. Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. Output drive source for the V2 regulator connected to the external series pass transistor. Supply input pin for the 33742. Output of the internal high-side switch. The output current is internally limited to 150 mA. Inputs from external switches or from logic circuitry. CAN high output pin. CAN low output pin. Clock input pin for the Serial Peripheral Interface (SPI). SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the highimpedance state. SPI data received by the 33742. The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted LOW, the 33742 is the selected device of the SPI bus. The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered. 33742 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS 48 47 46 45 44 43 42 41 40 39 38 37 NC NC NC NC GND GND GND GND NC NC NC NC NC SCLK MISO MOSI CS WDOG RXD TXD VDD RST INT NC 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 NC CANL CANH L3 L2 L1 L0 HS VSUP V2 CTRL V2 NC Figure 4. 33742 48-Pin Connections Table 3. 33742 48-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 22. Pin 1, 12-16, 21-25, 36-40, 45-48 2 3 4 5 6 7 8 9 10 11 17-20 41-44 Pin Name NC Formal Name No Connect No connection. Definition SCLK MISO MOSI CS WDOG Serial Data Clock Master In Slave Out Master Out Slave In Chip Select (Active LOW) Watchdog Output (Active LOW) Receive Data Transmit Data Voltage Digital Drain Reset Output (Active LOW) Interrupt Output (Active LOW) Ground RXD TXD VDD RST INT GND NC NC NC NC GND GND GND GND NC NC NC NC Clock input pin for the Serial Peripheral Interface (SPI). SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the highimpedance state. SPI data received by the 33742. The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted LOW, the 33742 is the selected device of the SPI bus. The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered. CAN bus receive data output pin. CAN bus transmit data input pin. 5.0 V regulator output pin. Supply pin for the MCU. This is the device reset output pin whose main function is to reset the MCU. This pin has an internal pullup current source to VDD. This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. These device ground pins are internally connected to the package lead frame to provide a 33742-to-PCB thermal path. 13 14 15 16 17 18 19 20 21 22 23 24 33742 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN CONNECTIONS Table 3. 33742 48-Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin description section beginning on page 22. Pin 26 27 28 29 30-33 34 35 Pin Name V2 V2CTRL VSUP HS L0- L3 CANH CANL Formal Name Voltage Source 2 Voltage Source 2 Control Voltage Supply High-Side Output Level 0 - 3 Inputs CAN High Output CAN Low Output Definition Sense input for the V2 regulator using an external series pass transistor. V2 is also the internal supply for the CAN transceiver. Output drive source for the V2 regulator connected to the external series pass transistor. Supply input pin for the 33742. Output of the internal high-side switch. The output current is internally limited to 150 mA. Inputs from external switches or from logic circuitry. CAN high output pin. CAN low output pin. 33742 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating ELECTRICAL RATINGS Power Supply Voltage at VSUP Continuous (Steady-State) Transient Voltage (Load Dump) Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT) Output Voltage at VDD Output Current at VDD HS Voltage Output Current ESD Capability, Human Body Model (1) HS, L0, L1, L2, L3, CANH, CANL pins All Other pins ESD Capability, Machine Model (1) Input Voltage/Current at L0, L1, L2, L3 DC Input Voltage DC Input Current Transient Input Voltage attached to external circuitry (2) CANL and CANH Continuous Voltage Continuous Current CANH and CANL Transient Voltage (Load Dump) (3) CANH and CANL Transient Voltage (3) VCANH/L ICANH/L VLDH/L VTRH/L - 27 to 40 200 40 ± 40 V mA V V VDCIN IDCIN VTRINEC - 0.3 to 40 ± 2.0 ± 100 V mA V VESD2 VHS IHS VESD1 ± 4000 ± 2000 ± 200 V - 0.3 to VSUP + 0.3 Internally Limited V A V VLOG VDD IDD VSUP - 0.3 to 27 - 0.3 to 40 - 0.3 to VDD + 0.3 0.0 to 5.3 Internally Limited V V A V Symbol Value Unit Notes 1. Testing done in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machin