Local Interconnect Network (LIN) Physical Interface

www.DataSheet4U.com Freescale Semiconductor Advance Information Document Number: MC33399 Rev. 8.0, 10/2006 Local Interconnect Network (LIN) Physical Interface Local Interconnect Network (LIN) is a serial communication protocol designed to support automotive networks in conjunction with Controller Area Network (CAN). As the lowest level of a hierarchical network, LIN enables cost-effective communication with sensors and actuators when all the features of CAN are not required. The 33399 is a Physical Layer component dedicated to automotive sub-bus applications. It offers speed communication from 1.0 kbps to 20 kbps, and up to 60 kbps for Programming Mode. It has two operating modes: Normal and Sleep. The 33399 supports LIN Protocol Specification 1.3. Features • Nominal Operation from VSUP 7.0 V to 18 V DC, Functional up to 27 V DC Battery Voltage and Capable of Handling 40 V During Load Dump • Active Bus Waveshaping to Minimize Radiated Emission • ± 5.0 kV ESD on LIN Bus Pin, ± 4.0 kV ESD on Other Pins • 30 kΩ Internal Pullup Resistor • Ground Shift Operation and Ground Disconnection Fail-Safe at Module Level • An Unpowered Node Does Not Disturb the Network • 20 µA in Sleep Mode • Wake-Up Capability from LIN Bus, MCU Command and Dedicated High Voltage Wake-Up Input (Interface to External Switch) • Interface to MCU with CMOS-Compatible I/O Pins • Control of External Voltage Regulator • Pb-FREE packaging designated by package code EF 33399 LIN PHYSICAL INTERFACE D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8 PIN SOICN ORDERING INFORMATION Device MC33399D/R2 - 40°C to 125°C MCZ33399EF/R2 8 SOICN Temperature Range (TA) Package V PWR Regulator 12 V 5.0 V 33399 VSUP INH EN WAKE GND MCU TXD RXD LIN LIN Bus Figure 1. 33399 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM WAKE VSUP INF EN Wake-Up VREG Control VREF Bias 30 kΩ Logic RXD Protection Receiver LIN TXD Driver GND Figure 2. 33399 Simplified Internal Block Diagram 33399 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS RXD EN WAKE TXD 1 2 3 4 8 7 6 5 INH VSUP LIN GND Figure 3. 33399 8-SOICN Pin Connections Table 1. 8-SOICN Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. Pin 1 2 3 4 5 6 7 8 Pin Name RXD EN WAKE Formal Name Data Output Enable Control Wake Input Data Input Ground LIN Bus Power Supply Inhibit Output Definition MCU interface that reports the state of the LIN bus voltage. Controls the operation mode of the interface. High voltage input used to wake up the device from the Sleep mode. MCU interface that controls the state of the LIN output. Device ground pin. Bidirectional pin that represents the single-wire bus transmitter and receiver. Device power supply pin. Controls an external switchable voltage regulator having an inhibit input. TXD GND LIN VSUP INH 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating ELECTRICAL RATINGS Power Supply Voltage Continuous Supply Voltage Transient Voltage (Load Dump) WAKE DC and Transient Voltage (Through a 33 kΩ Serial Resistor) Logic Voltage (RXD, TXD, EN Pins) LIN Pin DC Voltage Transient (Coupled Through 1.0 nF Capacitor) INH Voltage / Current DC Voltage ESD Voltage, Human Body Model (1) All Pins LIN Bus Pin with Respect to Ground ESD Voltage, Machine Model All Pins THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance, Junction to Ambient Peak Package Reflow Temperature During Reflow Thermal Shutdown Thermal Shutdown Hysteresis (2) (3) Symbol Value Unit VSUP 27 40 VWAKE VLOG VBUS - 18 to 40 - 150 to 100 - 18 to 40 - 0.3 to 5.5 V V V V VINH V ESD1 - 0.3 to VSUP + 0.3 V V ± 4000 ± 5000 V ESD2 ± 200 V °C TA TJ TSTG RθJA , TPPRT TSHUT THYST - 40 to 125 - 40 to 150 - 55 to 165 150 Note 3. 150 to 200 8.0 to 20 °C °C/W °C °C °C Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 220 pF, RZAP = 0 Ω). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33399 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic VSUP PIN (DEVICE POWER SUPPLY) Supply Voltage Range Supply Current in Sleep Mode VLIN > VSUP - 0.5 V, VSUP < 14 V 14 V < VSUP < 18 V Supply Current in Normal Mode Recessive State Dominant State, Total Bus Load > 500 Ω Supply Undervoltage Threshold RXD OUTPUT PIN (LOGIC) Low-Level Output Voltage IIN ≤ 1.5 mA High-Level Output Voltage IOUT ≤ 250 µΑ TXD INPUT PIN (LOGIC) Low-Level Input Voltage High-Level Input Voltage Input Voltage Threshold Hysteresis Pullup Current Source 1.0 V < VTXD < 4.0 V, VEN = 5.0 V EN INPUT PIN (LOGIC) Low-Level Input Voltage High-Level Input Voltage Input Voltage Threshold Hysteresis EN Low-Level Input Current VIN = 1.0 V High-Level Input Current VIN = 4.0 V Pulldown Current 1.0 V < EN < 4.0 V IPD — 20 — IIH — 20 40 µA VIL VIH VINHYST IIL 5.0 20 30 µA — 3.5 100 — — 480 1.5 — 800 V V mV µA VIL VIH VINHYST IPU - 50 — - 25 — 3.5 100 — — 550 1.5 — 800 V V mV µA VOL 0.0 VOH 3.75 — 5.25 — 0.9 V V IS(REC) IS(DOM) VSUP_UV — — 5.5 — — 6.4 2.0 3.0 6.8 V IS1 IS2 — — 20 — 50 150 mA VSUP 7.0 13.5 18 V µA Symbol Min Typ Max Unit 33399 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic LIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE) Low-Level Bus Voltage (Dominant State) TXD LOW, VLIN = 40 mA High-Level Voltage (Recessive State) TXD HIGH, IOUT = 1.0 µA Internal Pullup Resistor to VSUP (4) - 40°C ≤ TA ≤ 70°C 70°C < TA ≤ 125°C Current Limitation TXD LOW, VLIN = VSUP Leakage Current to GND Recessive State, VSUP - 0.3 V ≤ VLIN ≤ VSUP (4) Symbol Min Typ Max Unit VDOM 0.0 VREC 0.85 VSUP RPU 20 35 I LIM 50 I LEAK 0.0 - 40 — — V LINL 0 VSUP V LINH 0.6 VSUP V LINTH — V LINHYS 0.05 VSUP V LINWU 3.5 — 4.5 0.15 VSUP 6.0 VSUP/2 — — VSUP — 0.4 VSUP — — - 600 15 10 40 — — 150 200 30 49 47 60 — — — 1.4 V V kΩ mA µA VSUP Disconnected, -18 V ≤ VLIN ≤ 18 V (Excluding Internal Pullup Source) VSUP Disconnected, VLIN = -18 V (Including Internal Pullup Source) VSUP Disconnected, VLIN = +18 V (Including Internal Pullup Source) LIN Receiver, Low-Level Input Voltage TXD HIGH, RXD LOW LIN Receiver, High-Level Input Voltage TXD HIGH, RXD HIGH LIN Receiver Threshold Center (VLINH - VLINL) / 2 LIN Receiver Input Voltage Hysteresis VLINH - VLINL LIN Wake-Up Threshold Voltage INH OUTPUT PIN High-Level Voltage (Normal Mode) Leakage Current (Sleep Mode) 0 < VINH < VSUP WAKE INPUT PIN Typical Wake-Up Threshold (EN = 0 V, 7.0 V ≤ VSUP ≤ 18 V) (5) HIGH-to-LOW Transition LOW-to-HIGH Transition Wake-Up Threshold Hysteresis WAKE Input Current VWAKE ≤ 14 V VWAKE > 14 V VWUHYS I WU VWUTH VWUH I LEAK V V V V V VSUP - 0.8 — VSUP V µA 0 — 5.0 V 0.3 VSUP 0.4 VSUP 0.1 VSUP 0.43 VSUP 0.55 VSUP 0.16 VSUP 0.55 VSUP 0.65 VSUP 0.2 VSUP V µA — — 1.0 — 5.0 100 Notes 4. A diode structure is inserted with the pullup resistor to avoid parasitic current path from LIN to VSUP. 5. 33399 When VSUP is greater than 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V. 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic DIGITAL INTERFACE TIMING LIN Slew Rate (6) , (7) Falling Edge Rising Edge LIN Rise/Fall Symmetry (t RISE - t FALL) Driver Propagation Delay (8) , (9) Symbol Min Typ Max Unit V/µs t FALL t RISE t SYM 0.75 0.75 - 2.0 2.0 2.0 — 3.0 3.0 2.0 µs µs t TXDLINL t TXDLINH (9) , (10) TXD LOW-to-LIN LOW TXD HIGH-to-LIN HIGH Receiver Propagation Delay LIN LOW to RXD LOW LIN HIGH to RXD HIGH