(MC908GT8 / MC908GT16) Microcontrollers

MC68HC908GT16 MC68HC908GT8 Data Sheet M68HC08 Microcontrollers www.DataSheet4U.com MC68HC908GT16 Rev. 3 09/2004 freescale.com MC68HC908GT16 MC68HC908GT8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 2) Date March, 2002 Revision Level N/A Original release 7.2 Features — Corrected third bulleted item to reflect ±4 percent variability Figure 15-1. Forced Monitor Mode (Low) — Reworked for clarity Figure 15-2. Forced Monitor Mode (High) — Reworked for clarity May, 2002 Figure 15-3. Standard Monitor Mode — Reworked for clarity 1.0 Table 15-1. Monitor Mode Signal Requirements and Options — Reworked for clarity Figure 12-4. Port A I/O Circuit — Reworked to correct pullup resistor Figure 12-11. Port C I/O Circuit — Reworked to correct pullup resistor Figure 12-15. Port D I/O Circuit — Reworked to correct pullup resistor Description Page Number(s) N/A 75 211 211 212 214 143 148 151 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004. All rights reserved. MC68HC908GT16 • MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 3 Revision History Revision History (Sheet 2 of 2) Date Revision Level Description Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data register (SCIADAT) to reflect read-only status June, 2002 2.0 Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address location designator from $0018 to $000A Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address location designator from $0019 to $000B Reformatted to meet current publications standards 1.5.6 ADC Reference Pins (VREFH and VREFL) — Corrected connections 2.6.3 FLASH Page Erase Operation — Updated procedure 2.6.4 FLASH Mass Erase Operation — Updated procedure 2.6.5 FLASH Program/Read Operation — Updated procedure 2.6.6 FLASH Block Protection — Description updated for clarity 3.3.5 Conversion — Updated for clarity 3.6.3 ADC Voltage Reference High Pin (VREFH) — Corrected connections 3.6.4 ADC Voltage Reference Low Pin (VREFL) — Corrected connections 3.7.1 ADC Status and Control Register — Updated description of the COCO bit Chapter 4 Configuration Register (CONFIG) — Updated COP tmeout selections Chapter 4 Configuration Register (CONFIG) — Updted SSREC bit usage Chapter 5 Computer Operating Properly (COP) Module — Updated timeout selections Figure 5-1. COP Block Diagram — Updated illustration for clarity Table 6-1. Instruction Set Summary — Updated definitions for STOP and WAIT September, 2004 3.0 Figure 7-9. Code Example for Switching Clock Sources — Replaced example code Figure 7-10. Code Example for Enabling the Clock Monitor — Replaced example code Figure 14-18. ESCI Prescaler Register (SCPSC) — Corrected address location Chapter 15 System Integration Module (SIM) — Clarified SIM features and functionality 15.7.2 SIM Reset Status Register — Clarified SRSR operation Table 19-1. Monitor Mode Signal Requirements and Options — Reworked 19.2.1 Functional Description — Corrected Break description 19.3 Monitor Module (MON) — Reworked Chapter 20 Electrical Specifications — Revised/added tables: 20.5 5.0-V DC Electrical Characteristics 20.6 3.0-V DC Electrical Characteristics 20.7 Supply Current Characteristics 20.8 5-V Control Timing 20.9 3-V Control Timing 20.20 Memory Characteristics — Updated memory table Chapter 20 Electrical Specifications — Added figures: Figure 20-1. RST and IRQ Timing Figure 20-2. RST and IRQ Timing Page Number(s) 50 170 171 Throughout 24 39 40 41 43 50 51 51 52 55, 57 58 60 59 68 87 88 170 177, 180, 181, 182 192 245 235, 238 241 255 256 257 258 258 271 258 258 MC68HC908GT16 • MC68HC908GT8 Data Sheet, Rev. 3 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 4 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 5 Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 6 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chapter 7 Internal Clock Generator (ICG) Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 11 Low-Power Modes (MODES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Chapter 12 Input/Output (I/O) Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 13 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Chapter 14 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 147 Chapter 15 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 17 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Chapter 18 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 273 MC68HC908GT16 • MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 5 List of Chapters MC68HC908GT16 • MC68HC908GT8 Data Sheet, Rev. 3 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features of the MC68HC908GT16/MC68HC908GT8 . . . . . . . . . . . . . . . . . . . . . Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins (PTE4/OSC1 and PTE3/OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC and ICG Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Reference Pins (VREFH and VREFL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E I/O Pins (PTE4–PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 21 22 23 23 24 24 24 24 24 25 25 25 25 25 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 2.6.10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) .