(MC908GRxxA) Microcontrollers

MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A Data Sheet www.DataSheet4U.com M68HC08 Microcontrollers MC68HC908GR60A Rev. 5 04/2007 freescale.com MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006, 2007. All rights reserved. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date April, 2004 July, 2004 Revision Level N/A 1 Initial release 9.7.3 Keyboard Interrupt Polarity Register — Corrected description of KBIP7–KBIP0. Table 13-6. ESCI LIN Control Bits — Corrected Functionality definitions June, 2005 2 13.9.1 ESCI Arbiter Control Register — Corrected definition for ACLK bit. 13.9.3 Bit Time Measurement — Corrected description of ACLK bit. March, 2006 3 10.5 Clock Generator Module (CGM) — Updated description to remove erroneous information. Added 1.5.15 Unused Pin Termination 12.1 Introduction — Replaced note Table 13-6. ESCI LIN Control Bits — Corrected functionality column. The following sections were updated to show that a break interrupt inhibits input captures: 17.6 TIM1 During Break Interrupts 18.6 TIM2 During Break Interrupts 19.2.1.2 TIM During Break Interrupts Figure 19-10. Normal Monitor Mode Circuit and Figure 19-11. Forced Monitor Mode — Changed capacitor values 20.5 5.0-Vdc Electrical Characteristics — Updated minimum value for low-voltage inhibit, trip rising voltage (VTRIPR). 20.9.1 CGM Component Specifications — Updated values for feedback bias resistor Figure 2-2. Control, Status, and Data Registers — Replaced TBMCLKSEL with TMBCLKSEL to be compatible with development tool nomenclature Chapter 5 Configuration Register (CONFIG) — Replaced COPCLK with CGMXCLK 10.6.2 Stop Mode — Replaced COPCLK with CGMXCLK Figure 13-3. ESCI Module Block Diagram — Changed BUS_CLK to Bus Clock and deleted reference to 4x BUSCLK 13.4.2 Transmitter — Changed ESCIBDSRC to SCIBDSRC April, 2007 5 13.9.1 ESCI Arbiter Control Register and 13.9.3 Bit Time Measurement — Replaced one quarter with one half in the definition for ACLK = 1 Chapter 16 Timebase Module (TBM) — Replaced TBMCLKSEL with TMBCLKSEL to be compatible with development tool nomenclature 20.5 5.0-Vdc Electrical Characteristics and 20.6 3.3-Vdc Electrical Characteristics — Updated tables 20.9 Clock Generation Module (CGM) Characteristics — Updated section to include the following: 20.9.1 CGM Operating Conditions 20.9.2 CGM Component Information 20.9.3 CGM Acquisition/Lock Time Information MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 4 Freescale Semiconductor Description Page Number(s) N/A 119 174 179 180 122 28 131 174 July, 2006 4 233 251 264 269 279 284 33 90 89 91 122 154 156 179 180 222 223 279 281 284 284 285 List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 6 Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 11 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Chapter 12 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Chapter 13 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 151 Chapter 14 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Chapter 16 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Chapter 17 Timer Interface Module (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Chapter 18 Timer Interface Module (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 295 Appendix A MC68HC908GR48A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Appendix B MC68HC908GR32A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 5 List of Chapters MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL). . . . . . . . . . . . . . . . Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8) . . . . . . . . . . . . . . . . Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E I/O Pins (PTE5–PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . Port F I/O Pins (PTF7/T2CH5–PTF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port G I/O Pins (PTG7/AD23–PTBG0/AD16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 21 21 23 25 25 26 26 26 26 26 26 27 27 27 27 27 27 28 28 Chapter 2 Memory 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 FLASH-1 Memo