Microcontrollers

www.DataSheet4U.com MC68HC908SR12 MC68HC08SR12 Data Sheet M68HC08 Microcontrollers MC68HC908SR12 Rev. 5.0 07/2004 freescale.com MC68HC908SR12 MC68HC08SR12 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Data Sheet 3 Revision History Revision History Date Revision Level Description Table 24-2 . Operating Range and Table 24-11 . 3V ADC Electrical Characteristics — changed minimum VDD for ADC operation to 3V. 15.8.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3) — Corrected ADRL–ADRL3 register bits. PTB0/SDA0, PTB1/SCL0, PTB2/SDA1/TxD, and PTB3/SCL1/RxD pins — clarified these open-drain pins throughout this document. 8.4.6 Programming the PLL — deleted redundant step in programming the PLL. Figure 10-1 . Monitor Mode Circuit — corrected connections for PTA1 and PTA2. Table 10-1 . Monitor Mode Signal Requirements and Options — clarified clock input requirements for monitor mode entry. Section 11. Timer Interface Module (TIM) — timer discrepancies corrected throughout this section. February, 2002 4 18.5.1 Port C Data Register (PTC) and 18.5.2 Data Direction Register C (DDRC) — added notes for PTC6 and PTC7 on 42-pin package. Figure 19-3 . IRQ2 Block Diagram and 19.5 IRQ1 and IRQ2 Pins — corrected IRQ2 for BIH and BIL instructions. Table 24-4 . 5V DC Electrical Characteristics and Table 24-5 . 3V DC Electrical Characteristics — added additional IDD measurements. Table 24-13 . Current Detection Electrical Characteristics — updated trip point values. Appendix A. MC68HC08SR12 — added appendix for ROM part: MC68HC08SR12. Page Number(s) 373, 381 July 2004 5 248 323, 254, 293 120 167 169 181 327, 329 338, 339 374, 376 382 393 Data Sheet 4 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Data Sheet — MC68HC908SR12•MC68HC08SR12 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 35 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 61 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. Configuration and Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . . . . . . . . . . 73 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 81 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . 101 Section 8. Clock Generator Module (CGM) . . . . . . . . . . 111 Section 9. System Integration Module (SIM) . . . . . . . . 141 Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 165 Section 11. Timer Interface Module (TIM) . . . . . . . . . . . 181 Section 12. Timebase Module (TBM) . . . . . . . . . . . . . . . 205 Section 13. Pulse Width Modulator (PWM) . . . . . . . . . . 211 Section 14. Analog Module . . . . . . . . . . . . . . . . . . . . . . 221 Section 15. Analog-to-Digital Converter (ADC) . . . . . . 231 Section 16. Serial Communications Interface (SCI) . . . 251 Section 17. Multi-Master IIC Interface (MMIIC) . . . . . . . 291 Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 317 Section 19. External Interrupt (IRQ) . . . . . . . . . . . . . . . 335 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor List of Sections Data Sheet 5 List of Sections Section 20. Keyboard Interrupt Module (KBI). . . . . . . . 343 Section 21. Computer Operating Properly (COP) . . . . 351 Section 22. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 357 Section 23. Break Module (BRK) . . . . . . . . . . . . . . . . . . 363 Section 24. Electrical Specifications. . . . . . . . . . . . . . . 371 Section 25. Mechanical Specifications . . . . . . . . . . . . . 387 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 391 Appendix A. MC68HC08SR12 . . . . . . . . . . . . . . . . . . . . 393 Data Sheet 6 List of Sections MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Data Sheet — MC68HC908SR12•MC68HC08SR12 Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 1.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 1.6.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 42 1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 42 1.6.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.4 External Interrupt Pin (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . .43 1.6.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . .43 1.6.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.6.7 ADC Voltage Low Reference Pin (VREFL) . . . . . . . . . . . . . . 43 1.6.8 ADC Voltage High Reference Pin (VREFH). . . . . . . . . . . . . . 43 1.6.9 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 43 1.6.10 Analog Input Pins (OPIN1/ATD0, OPIN2/ATD1, VSSAM) . . . 44 1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . . 44 1.6.12 Port B I/O Pins (PTB6–PTB0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.13 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 44 1.6.14 Port D I/O Pins (PTD7/KBI7–PTD0/KBI0) . . . . . . . . . . . . . . 44 Section 2. Memory Map 2.1 2.2 2.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 45 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Freescale Semiconductor Table of Contents Data Sheet 7 Table of Contents 2.4 2.5 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Section 3. Random-Access Memory (RAM) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Section 4. FLASH Memory 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 66 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 67 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4.8 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 70 Section 5. Configuration and Mask Option Registers (CONFIG & MOR) 5.1 5.2 5.3 5.4 5.5 5.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 75 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 77 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Data Sheet 8 MC68HC908SR12•MC68HC08SR12 — Rev. 5.0 Table of Contents Freescale Semiconductor Table of Contents Section 6. Central Processor Unit (CPU) 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.6.1 Wait Mode . . . . . . . . . . . . . .