Microcontrollers

www.DataSheet4U.com MC68HC908MR8 Technical Data M68HC08 Microcontrollers Rev. 4.1 MC68HC908MR8/D August 16, 2005 freescale.com MC68HC908MR8 Technical Data — Rev 4.0 Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc. is an Equal Opportunity/Affirmative Action Employer. © Freescale, Inc., 2005 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Technical Data 3 Technical Data 4 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Technical Data — MC68HC908MR8 List of Paragraphs Section 1. General Description . . . . . . . . . . . . . . . . . . . . 29 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 53 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 55 Section 5. Configuration Register (CONFIG) . . . . . . . . . 67 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 71 Section 7. System Integration Module (SIM) . . . . . . . . . 89 Section 8. Clock Generator Module (CGM) . . . . . . . . . . 111 Section 9. Pulse-Width Modulator for Motor Control (PWMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 187 Section 11. Timer Interface A (TIMA). . . . . . . . . . . . . . . 199 Section 12. Timer Interface B (TIMB). . . . . . . . . . . . . . . 223 Section 13. Serial Communications Interface (SCI) . . . 247 Section 14. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 279 Section 15. Computer Operating Properly (COP) . . . . 291 Section 16. External Interrupt (IRQ) . . . . . . . . . . . . . . . 297 Section 17. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 305 Section 18. Analog-to-Digital Converter (ADC) . . . . . . 311 Section 19. Power-On Reset (POR) . . . . . . . . . . . . . . . 327 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor List of Paragraphs Technical Data 5 List of Paragraphs Section 20. Break (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . 329 Section 21. Electrical Specifications. . . . . . . . . . . . . . . 339 Section 22. Mechanical Specifications . . . . . . . . . . . . . 351 Section 23. Ordering Information . . . . . . . . . . . . . . . . . 355 Technical Data — Revision History . . . . . . . . . . . . . . . . 357 Technical Data 6 List of Paragraphs MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Technical Data — MC68HC908MR8 Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.5.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . 34 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 34 1.5.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5.5 CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . 35 1.5.6 ADC Reference Voltage Input Pin (VREFH) . . . . . . . . . . . . . 35 1.5.7 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . 35 1.5.8 Port A Input/Output (I/O) Pins (PTA6/ATD6–PTA0/ATD0). . 35 1.5.9 Port B I/O Pins (PTB6/TCHB1–PTB0/RxD) . . . . . . . . . . . . . 36 1.5.10 Port C I/O Pins (PTC1/FAULT1–PTC0/FAULT4). . . . . . . . . 36 1.5.11 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . . 36 Section 2. Memory Map 2.1 2.2 2.3 2.4 2.5 2.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 38 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Table of Contents Technical Data 7 Table of Contents Section 3. Random-Access Memory (RAM) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Section 4. FLASH Memory 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.2.3 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.4 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.5 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . .59 4.3 FLASH Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.1 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.3.2 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Section 5. Configuration Register (CONFIG) 5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CONFIG Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Section 6. Central Processor Unit (CPU) 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Technical Data 8 Table of Contents MC68HC908MR8 — Rev 4.1 Freescale Semiconductor Table of Contents 6.4.4 6.4.5 6.5 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.7 6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Section 7. System Integration Module (SIM) 7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 93 7.3.1 Bus Timing