CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR

www.DataSheet4U.com Order this document by MC34115/D MC34115 Continuously Variable Slope Delta Modulator/Demodulator CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR SEMICONDUCTOR TECHNICAL DATA Providing a simplified approach to digital speech encoding/decoding, the MC34115 CVSD is designed for speech synthesis and commercial telephone applications. A single IC provides both encoding and decoding functions. • Encode and Decode Functions Selectable with a Digital Input • Utilization of Compatible I2L – Linear Bipolar Technology • • • CMOS Compatible Digital Output Digital Input Threshold Selectable (VCC/2 Reference Provided On–Chip) 3–Bit Algorithm 16 1 P SUFFIX PLASTIC PACKAGE CASE 648 16 CVSD Block Diagram Encode/Decode 15 Analog Input Analog Feedback 1 2 – + Clock 14 VCC 16 1 DW SUFFIX PLASTIC PACKAGE CASE 751G (SO–16L) Digital 13 Data Input Digital 12 Threshold PIN CONNECTIONS – + Vth 3–Bit Shift Register QQQQQQ Analog Input (–) 1 Analog Feedback (+) 2 Syllabic Filter 3 Gain Control 4 Logic 11 Coincidence Output V/I Converter Slope Polarity Switch IInt 6 Filter Input (–) 8 VEE Ref Input (+) 5 Filter Input (–) 6 Analog Output 3 4 Syllabic Filter Gain Control IGC VEE 7 8 (Top View) 16 VCC 15 Encode/Decode 14 Clock 13 Digital Data Input (–) 12 Digital Threshold 11 Coincidence Output 10 VCC/2 Output 9 Digital Output Digital Output VCC/2 Output 9 10 IRef IO 7 Analog Output VCC/2 Ref Integrator Amplifier – + 5 Ref Input (+) ORDERING INFORMATION Device MC34115P Operating Temperature Range TA = 0° to +70°C Package Plastic DIP SO–16L Rev 1 This device contains 144 active transistors. MC34115DW © Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA 1 MC34115 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ unless otherwise noted.) (Note 2) Rating Symbol VCC VID Vth Value Unit Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc mA °C °C °C Power Supply Voltage –0.4 to +18 ±5.0 Differential Analog Input Voltage Digital Threshold Voltage –0.4 to VCC –0.4 to +18 –0.4 to +18 Logic Input Voltage (Clock, Digital Data, Encode/Decode) Coincidence Output Voltage Syllabic Filter Input Voltage Gain Control Input Voltage Reference Input Voltage VCC/2 Output Current VLogic VO(Con) VI(Syl) –0.4 to VCC –0.4 to VCC VI(GC) VI(ref) Iref TA TJ VCC/2 – 1.0 to VCC –25 Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature Range 0 to +70 +150 Tstg –55 to +125 NOTE: ESD data available upon request. MAXIMUM RATINGS (All voltages referenced to VEE, TA = 25°C, ELECTRICAL CHARACTERISTICS (VCC = 12 V, VEE = Gnd, TA = 0° to 70°C, unless otherwise noted.) Characteristic Power Supply Voltage Range (Figure 1) Power Supply Current (Figure 1) (Idle Channel) VCC = 5.0 V VCC = 15 V Clock Rate Gain Control Current Range (Figure 2) Analog Comparator Input Range (Pins 1 and 2) 4.75 V ≤ VCC ≤ 16.5 V Analog Output Range (Pin 7) 4.75 V ≤ VCC ≤ 16.5 V, IO = ±5.0 mA Input Bias Currents (Figure 3) Comparator in Active Region Analog Input (I1) Analog Feedback (I2) Syllabic Filter Input (I3) Reference Input (I5) Input Offset Current Comparator in Active Region Analog Input/Analog Feedback I1 – I2 (Figure 3) Integrator Amplifier I5 – I6 (Figure 4) Input Offset Voltage V/I Converter (Pins 3 and 4) (Figure 5) Transconductance V/I Converter, 0 to 3.0 mA Integrator Amplifier, 0 to +5.0 mA Load Symbol VCC ICC – – SR IGCR VI VO IIB – – – – IIO – – VIO gm 0.1 1.0 0.3 10 – – – 0.15 0.02 2.0 0.8 0.2 10 mV mA/mV 0.5 0.5 0.06 –0.06 2.5 2.5 0.5 –0.5 µA – 0.002 1.3 1.3 4.6 7.0 16 k – – – 7.5 12 – 3.0 VCC – 1.3 VCC – 1.3 Samples/s mA Vdc Vdc µA Min 4.75 Typ 12 Max 16.5 Unit Vdc mA NOTES: 1. All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock. 2. Devices should not be operated at these values. The “Electrical Characteristics” provide conditions for actual device operation. 3. Dynamic total loop offset (ΣVoffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch current mismatch appears as an average voltage across the 10 k integrator resistor. The clock frequency is 16 kHz. Idle channel performance is guaranteed if this dynamic total loop offset is less than one–half of the change in integrator output voltage during one clock cycle (ramp step size). 2 MOTOROLA ANALOG IC DEVICE DATA MC34115 ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V, VEE = Gnd, TA = 0° to 70°C, unless otherwise noted.) Characteristic Propagation Delay Times (Note 1) Clock Trigger to Digital Output CL = 25 pF to Gnd Clock Trigger to Coincidence Output CL = 25 pF to Gnd, RL = 4.0 kΩ to VCC Coincidence Output Voltage – Low Logic Stage (IOL(Con) = 3.0 mA) Coincidence Output Leakage Current – High Logic State (VOH = 15 V) Applied Digital Threshold Voltage Range (Pin 12) Digital Threshold Input Current 1.2 V ≤ Vth ≤ VCC – 2.0 V VIL Applied to Pins 13, 14 and 15 VIH Applied to Pins 13, 14 and 15 Maximum Integrator Amplifier Output Current VCC/2 Generator Maximum Output Current (Source Only) VCC/2 Generator Output Impedance (0 to –10 mA) VCC/2 Generator Tolerance (4.75 V ≤ VCC ≤ 16.5 V) Logic Input Voltage (Pins 13, 14 and 15) Low Logic State High Logic State Dynamic Total Loop Offset Voltage (Note 3) (Figures 3, 4 and 5) IGC = 33 µA, VCC = 12 V TA = 25°C 0°C ≤ TA ≤ +70°C IGC = 33 µA, VCC = 5.0 V TA = 25°C 0°C ≤ TA ≤ +70°C Digital Output Voltage (Pin 9) IOL = 3.6 mA IOH = –0.35 mA Syllabic Filter Applied Voltage (Pin 3) (Figure 2) Integrating Current (Figure 2) IGC = 12 µA IGC = 1.5 mA IGC = 3.0 mA Dynamic Integrating Current Match (Figure 6) (IGC = 1.5 mA) Input Current – High Logic State (VIH = 16.5 V) Digital Data Input Clock Input Encode/Decode Input Input Current – Low Logic State (VIL = 0 V) Digital Data Input Clock Input Encode/Decode Input Clock Input, VIL = 0.4 V Symbol tPLH tPHL tPLH tPHL VOL(Con) IOH(Con) Vth II(th) – – IO Iref zref εr VIL VIH ΣVoffset – – – – VOL VOH VI(Syl) IInt 8.0 1.4 2.75 VO(Ave) IIH – – – IIL –10 –360 –36 –72 – – – – – – – – – – – 5.0 5.0 5.0 µA – 10 1.5 3.0 ±100 12 1.6 3.25 ±300 – VCC – 1.0 3.2 ±2.5 ±3.0 ±4.0 ±4.5 0.1 VCC – 0.2 – ±7.0 ±10 ±8.0 ±12 Vdc 0.4 – VCC Vdc µA mA mA mV µA ±5.0 –10 – – VEE Vth + 0.4 – –10 – – 3.0 – – – 5.0 –50 – – 6.0 ±3.5 Vth – 0.4 16.5 mV mA mA Ω % Vdc Min – – – – – – 1.2 Typ 1.0 0.8 1.0 0.8 0.12 0.01 – Max 3.0 3.0 3.5 2.5 0.25 0.5 VCC – 2.0 Vdc µA Vdc µA Unit µs NOTES: 1. All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock. 2. Devices should not be operated at these values. The “Electrical Characteristics” provide conditions for actual device operation. 3. Dynamic total loop offset (ΣVoffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog