PLL Tuned UHF Receiver

Freescale Semiconductor Data Sheet MC33596 Rev. 3, 06/2007 MC33596 PLL Tuned UHF Receiver for Data Transfer Applications 1 Overview GNDSUBD The MC33596 is a highly integrated receiver designed for low-voltage applications. It includes a programmable PLL for multi-channel applications, an RSSI circuit, a strobe oscillator that periodically wakes up the receiver while a data manager checks the content of incoming messages. A configuration www.DataSheet4U.com switching feature allows automatic changing of the configuration between two programmable settings without the need of an MCU. LQFP32 QFN32 STROBE SWITCH VCC2IN 2 Features RSSIOUT VCC2RF RFIN GNDLNA VCC2VCO GND NC GND 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 General: • 304 MHz, 315 MHz, 426 MHz, 434 MHz, 868 MHz, and 915 MHz ISM bands • Choice of temperature ranges: — –40°C to +85°C — –20°C to +85°C • OOK and FSK reception • • • • 20 kbps maximum data rate using Manchester coding 2.1 V to 3.6 V or 5 V supply voltage Programmable via SPI 6 kHz PLL frequency step GNDIO VCCIN GND NC SEB SCLK MOSI MISO CONFB DATACLK RSSIC GNDDIG 10 11 12 13 14 VCCDIG VCC2OUT RBGAP 15 9 XTAL0UT © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. VCCINOUT VCCDIG2 XTALIN GND 16 Features • • Current consumption: — 10.3 mA in RX mode — Less then 1 mA in RX mode with strobe ratio = 1/10 — 260 nA standby and 24 μA off currents Configuration switching — allows fast switching of two register banks Receiver: • –106.5 dBm sensitivity, up to –108 dBm in FSK 2.4 kbps • Digital and analog RSSI (received signal strength indicator) • Automatic wakeup function (strobe oscillator) • Embedded data processor with programmable word recognition • Image cancelling mixer • • 380 kHz IF filter bandwidth Fast wakeup time Ordering information Temperature Range –40°C to +85°C –20°C to +85°C QFN Package MC33596FCE/R2 MC33596FCAE/R2 LQFP Package MC33596FJE/R2 MC33596FJAE/R2 MC33596 Data Sheet, Rev. 3 2 Freescale Semiconductor Pre Regulator RSSI_8BITS VCCIN VCCINOUT BAND BAND Freescale Semiconductor Analog Test ANALOG_SIGNALS Logarithmic Amplifier RSSI 4 Bits A/D Strobe Oscillator V&I Reference Voltage Regulator VCC2OUT VCC2IN RBGAP STROBE TEST_CONTROL ACCLNA PMA + I/Q Image Reject 1.5 MHz, BW 400 kHz AGC GAIN_SET AGC_CONTROL FM-to-AM Converter DATA_RATE AGC_CONTROL FM_AM SWITCH_TESTOUT State Machine IF Amplifier Detector Analog Data Filter and Slicer Rx Data Manager SPI MOSI MISO SCLK SEB RSSIC BAND BAND IF_REF_CLOCK PFD XCO Clock Generator DATACLK DIG_CLOCK XTALOUT XTALIN VCCDIG Fractional Divider Voltage Regulator VCCDIG2 CONFB GND GND GNDDIG GNDIO GNDSUBD GNDSUBA /2 VCO RSSIOUT_TESTIN SWITCH_TESTOUT VCC2RF RFIN LIN +I/Q Mixers GNDLNA Figure 1. Block Diagram MC33596 Data Sheet, Rev. 3 VCC2VC0 /2 or Buffer Features 3 Pin Functions 3 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Functions Table 1. Pin Functions Name RSSIOUT VCC2RF RFIN GNDLNA VCC2VCO GND NC GND XTALIN XTALOUT VCCINOUT VCC2OUT VCCDIG VCCDIG2 RBGAP GND GNDDIG RSSIC DATACLK CONFB MISO MOSI SCLK SEB GNDIO VCCIN NC STROBE GNDSUBD VCC2IN SWITCH GND RSSI analog output 2.1 V to 2.7 V internal supply for LNA RF input Ground for LNA (low noise amplifier) 2.1 V to 2.7 V internal supply for VCO Ground Not connected Ground Crystal oscillator input Crystal oscillator output 2.1 V to 3.6 V power supply/regulator output 2.1 V to 2.7 V voltage regulator output for analog and RF modules 2.1 V to 3.6 V power supply for voltage limiter 1.5 V voltage limiter output for digital module Reference voltage load resistance General ground Digital module ground RSSI control input Data clock output to microcontroller Configuration mode selection input Digital interface I/O Digital interface I/O Digital interface clock I/O Digital interface enable input Digital I/O ground 2.1 V to 3.6 V or 5.5 V input No connection Strobe oscillator capacitor or external control input Ground 2.1 V to 2.7 V power supply for analog modules for decoupling capacitor RF switch control output General ground Description MC33596 Data Sheet, Rev. 3 4 Freescale Semiconductor Silicon Version 4 5 Silicon Version Maximum Ratings Table 2. Maximum Ratings Parameter Symbol VCCIN VCC VCC2 — VCCIO — — — TS TJ Value VGND–0.3 to 5.5 VGND–0.3 to 3.6 VGND–0.3 to 2.7 VGND–0.3 to VCC2 VGND–0.3 to VCCIN+0.3 ±2000 ±200 260 –65 to +150 150 Unit V V V V V V V °C °C °C This data sheet describes the functional features of silicon version ES4.1. Supply voltage on pin: VCCIN Supply voltage on pins: VCCINOUT, VCCDIG Supply voltage on pins: VCC2IN, VCC2RF, VCC2VCO Voltage allowed on each pin (except digital pins) Voltage allowed on digital pins: SEB, SCLK, MISO, MOSI, CONFB, DATACLK, RSSIC, STROBE ESD HBM voltage capability on each pin1 ESD MM voltage capability on each Solder heat resistance test (10 s) Storage temperature Junction temperature NOTES: 1 Human body model, AEC-Q100-002 rev. C. 2 Machine model, AEC-Q100-003 rev. C. pin2 MC33596 Data Sheet, Rev. 3 Freescale Semiconductor 5 Power Supply 6 Power Supply Table 3. Supply Voltage Range Versus Ambient Temperature Temperature Range1 Parameter Symbol –40°C to +85°C –20°C to +85°C 2.1 to 3.6 4.5 to 5.5 V V VCC3V VCC5V 2.7 to 3.6 4.5 to 5.5 Unit Supply voltage on VCCIN, VCCINOUT, VCCDIG for 3 V operation Supply voltage on VCCIN for 5 V operation NOTES: 1 –40°C to +85°C: MC33596FCE/FJE. –20°C to +85°C: MC33596FCAE/FJAE. The circuit can be supplied from a 3 V voltage regulator or battery cell by connecting VCCIN and VCCINOUT. It is also possible to use a 5 V power supply connected to VCCIN; in this case VCCINOUT should not be connected to VCCIN. An on-chip low drop-out voltage regulator supplies the RF and analog modules (except the strobe oscillator and the low voltage detector, which are directly supplied from VCCINOUT). This voltage regulator is supplied from pin VCCINOUT and its output is connected to VCC2OUT. An external capacitor must be inserted between VCC2OUT and GND for stabilization and decoupling. The analog and RF modules must be supplied by VCC2 by externally wiring VCC2OUT to VCC2IN, VCC2RF and VCC2VCO. VCC2 32 31 30 29 28 27 26 25 3V 5V 28 27 26 25 GNDIO VCC2 32 31 30 29 SWITCH GNDSUBD STROBE VCC2IN GNDIO GND VCCIN NC SWITCH GNDSUBD STROBE GND VCC2IN 1 VCC2 2 3 4 VCC2 5 6 7 8 RSSIOUT VCC2RF RFIN GNDLNA SEB SCLK MOSI 24 23 22 21 20 19 18 17 VCC2 VCC2 VCCIN NC 1 2 3 4 5 6 7 8 RSSIOUT VCC2RF RFIN GNDLNA SEB SCLK MOSI 24 23 22 21 20 19 18 17 VCC2VCO GND NC VCCNOUT U15 MC33596 MISO CONFB DATACLK RSSIC VCC2VCO GND VCCINOUT NC XTAL0UT GND XTALIN U14 MC33596 MISO CONFB DATACLK RSSIC VCC2OUT VCC2OUT VCCDIG2 XTAL0UT VCCDIG2 VCCDIG GND XTALIN GNDDIG RBGAP GND VCCDIG GNDDIG RBGAP GND 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 VCC2 VCC2 3-V Operation 5-V Operation Figure 2. Wiring Diagrams A second voltage regulator supplies the digital part. This regulator is powered from pin VCCDIG and its output is connected to VCCDIG2. An external capacitor must be inserted between VCCDIG2 and MC33596 Data Sheet, Rev. 3 6 Freescale Semiconductor 16 Supply Voltage Monitoring and Reset GNDDIG, for decoupling. The supply voltage VCCDIG2 is equal to 1.6 V. In standby mode, this voltage regulator goes into an ultra-low-power mode, but VCCDIG2 = 0.7 x VCCDIG. This enables the internal registers to be supplied, allowing configuration data to be saved. 7 Supply Voltage Monitoring and Reset At power-on, an internal reset signal is generated. All registers are reset. When the LVDE bit is set, the low-voltage detection module is enabled. This block compares the supply voltage on VCCINOUT with a reference level of about 1.8 V. If the voltage on VCCINOUT drops below 1.8 V, status bit LVDS is set. The information in status bit LVDS is latched and reset after a read access. NOTE If LVDE = 1, the LVD module remains enabled. The circuit cannot be put in standby mode, but remains in LVD mode with a higher quiescent current, due to the monitoring circuitry. LVD function is not accurate in standby mode. 8 Receiver Functional Description The receiver is based on a superheterodyne architecture with an intermediate frequency (IF) of 1.5 MHz (see Figure 1). Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side injection I/Q mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection of the image frequency. The low intermediate frequency allows integration of the IF filter providing the selectivity. The center frequency is tuned by automatic frequency control (AFC) referenced to the crystal oscillator frequency. Sensitivity is met by an overall amplification of approximately 96 dB, distributed over the reception chain, comprising low-noise amplifier (LNA), mixer, post-mixer amplifier, and IF amplifier. Automatic gain control (AGC), on the LNA and the IF amplifier, maintains linearity and prevents internal saturation. Sensitivity can be reduced using four programmable steps on the LNA gain. Amplitude demodulation is achieved by peak detection and comparison with a fixed or adaptive voltage reference selected during configuration. Frequency demodulation is achieved in two steps: the IF amplifier AGC is disabled and acts as an amplitude limiter; a filter performs a frequency-to-voltage conversion. The resulting signal is then amplitude demodulated in the same way as in the case of amplitude modulation with an adaptive voltage reference. A low-pass filter improves the signal-to-noise ratio. Shaped data are available if the integrated data manager is not used. If used, the data manager performs clock recovery and decoding of Manchester coded data. Data and clock are then available on the serial periphe