PLL Tuned UHF Receiver

MOTOROLA SEMICONDUCTOR TECHNICAL Freescale Semiconductor, Inc. Order this document by MC33593/D ROMEO2 MC33593 PLL Tuned UHF Receiver for Data Transfer Applications • • • • • • • • • • • • • • • 868MHz, 902-928MHz Bands OOK and FSK Demodulation Low Current Consumption: 7mA Typ. in Run Mode Internal or External Strobing Fast Wake-Up Time (1ms) -105dBm RF Sensitivity (at 4.8kBd Data Rate) Fully Integrated VCO Image Cancelling Mixer Integrated IF Bandpass Filter at 660kHz IF Bandwidth: 500kHz ID Byte and Tone Detection Data Rate: 1 to 11kBd Manchester Coded Data Clock Recovery Fully Configurable by SPI Interface Few External Components, no RF Adjustment Pin Connections RCBGAP STROBE GNDDIG MIXOUT CAFC 24 VCC 1 VCC 2 VCCLNA 3 RFIN 4 GNDLNA 5 GNDSUB 6 23 22 21 20 19 18 VCCDIG 17 SCLK 16 MOSI 15 MISO 14 RESETB 13 DMDAT 7 PFD 8 GNDVCO 9 GND 10 XTAL1 11 XTAL2 12 CAGC www.DataSheet4U.com Figure 1: Simplified block diagram Table 1: Ordering Information Device MC33593FTA RF frequency/ IF filter bandwidth 868MHz / 500kHz Ambiant Temperature Range -40°C to +85°C Package LQFP24 This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 7.0 © Motorola, Inc., 2002. For More Information On This Product, Go to: www.freescale.com Non Disclosure Agreement Required CMIXAGC Freescale Semiconductor, Inc... MC33593 Freescale Semiconductor, Inc. PIN FUNCTION DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VCC VCC VCCLNA RFIN GNDLNA GNDSUB PFD GNDVCO GND XTAL1 XTAL2 CAGC DMDAT RESETB MISO MOSI SCLK VCCDIG GNDDIG RCBGAP STROBE CAFC MIXOUT CMIXAGC Description 5V power supply 5V power supply 5V LNA power supply RF input LNA ground Ground Access to VCO control voltage VCO ground Ground Reference oscillator crystal Reference oscillator crystal IF AGC capacitor for OOK Reference for FSK Demodulated data (OOK & FSK modulation) State Machine Reset SPI interface I/O SPI interface I/O SPI interface clock 5V digital power supply Digital ground Reference voltage output Strobe oscillator control Stop/Run external control input AFC capacitor Mixer output Mixer AGC capacitor © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS For More Information On This Product, 2 Go to: www.freescale.com revision 7.0, 5 February 2002 Non Disclosure Agreement Required Freescale Semiconductor, Inc... MC33593 Freescale Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Voltage Allowed on Each Pin ESD HBM Voltage Capability on Each Pin (note 1) ESD MM Voltage Capability on Each Pin (note 2) Solder Heat Resistance Test (10 s) Storage Temperature Junction Temperature Notes: 1 Human Body model, AEC-Q100-002 Rev. C. 2 Machine Model, AEC-Q100-003 Rev. E. Symbol VCC VCCLNA Value VGND - 0.3 to 5.5 VGND - 0.3 to VCC + 0.3 ±2000 ±200 260 Unit V V V V °C °C °C Ts Tj -65 to +150 150 © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS For More Information On This Product, 3 Go to: www.freescale.com revision 7.0, 5 February 2002 Non Disclosure Agreement Required Freescale Semiconductor, Inc... MC33593 Freescale Semiconductor, Inc. RECEIVER FUNCTIONAL DESCRIPTION The basic functionality of the ROMEO2 receiver may be seen by reference to the accompanying block diagram (see figure 1). It is fully compatible with the TANGO3 transmitter. The RF section comprises a mixer with image cancelling, followed by an IF band-pass filter at 660kHz, an AGC controlled gain stage and OOK and FSK demodulators, the desired modulation type being selectable by the SPI interface. The data output from the circuit may either be the data comparator output, or, if Data Manager is enabled, the SPI port. The local oscillator is controlled with a PLL referenced to the crystal oscillator. The received channel is defined by the choice of the crystal frequency. An SPI bus permits programming the modulation type, data rate, UHF frequency, ID word etc., though to accomodate applications where no bus interface is available the circuit defaults at power-on to a standard operating mode. THE LOCAL OSCILLATOR PLL The PLL is tuned by comparing the local oscillator frequency, after suitable division, with that of the crystal oscillator reference. The loop filter has been integrated in the IC. Practical limits upon the values of components which may be integrated mean that the local oscillator performance may be slightly improved by using an external PFD filter, shown in Figure 2. In this way the user may choose to have optimum performance with the addition of external filter components. The PLL gain may be programmed by bit PG: it is recommended that this bit be set to 1, corresponding to low loop gain. Figure 2 : External loop filter C1=4.7nF, C2=390pF, R=1kΩ © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS For More Information On This Product, 4 Go to: www.freescale.com revision 7.0, 5 February 2002 Non Disclosure Agreement Required Freescale Semiconductor, Inc... Depending upon the configuration, the circuit can be either externally strobed by the STROBE input or internally wait-and-sleep cycled to reduce the power consumption. At any time, a high level on STROBE overrides the internal timer output and wakes up ROMEO2. When the circuit is switched into sleep mode its current consumption is approximately 100µA. The circuit configuration which has previously been programmed is retained. MC33593 Freescale Semiconductor, Inc. COMMUNICATION PROTOCOL MANCHESTER CODING DESCRIPTION Manchester coding is defined as follows: data is sent during the first half-bit, complementary data is sent during the second half-bit. Figure 3: Manchester coding example 0 1 0 0 1 1 0 Original data Manchester coded PREAMBLE, ID, HEADER WORDS AND MESSAGE DESCRIPTION The following description applies if the Data Manager is enabled (DME=1). The ID word is a Manchester coded byte whose content has been previously loaded in the Configuration Register 2. The complement of the ID word is recognized as an ID word. ID word is sent at the same data rate as data. A preamble is required: - before ID, - before Header if HE=1, - before data if HE=0. It enables: - in case of OOK modulation, AGC to settle, - in case of FSK modulation, data slicer reference voltage to settle, - in any case, clock recovery. Figure 4 defines the Preamble word in OOK and FSK modulation. Preamble content must be carefully defined in order not to be decoded as an ID or Header word. Figure 4: Preamble definition OOK Modulation: AGC settling time Clock recovery ID ‘1’ NRZ > 200µs i.e.: 2 ‘1’ NRZ at 9.6kBd, 1 ‘1’ NRZ at 4.8kBd ‘0’ Manchester at data rate FSK Modulation: Data slicer reference settling time Clock recovery ID 3 ‘1’ or ‘0’ Manchester at data rate ‘1’ or ‘0’ Manchester at data rate The Header word is a 4 bit Manchester coded message ‘0110’ or its complement sent at the selected data rate. This bit sequence and its complement must not be found in the sequence preamble and ID word. Data must follow the Header without any delay. Data are completed by a End-of-Message (EOM) word, consisting of 2 NRZ consecutive ones or zeroes. Even in case of FSK modulation, the data must be completed by a EOM and not by simply stopping the RF telegram. If the complement of the Header word is received, output data are complemented too. © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS For More Information On This Product, 5 Go to: www.freescale.com revision 7.0, 5 February 2002 Non Disclosure Agreement Required Freescale Semiconductor, Inc... The signal average value is constant. This allows clock recovery from the data stream itself. In order to achieve a correct clock recovery, Manchester coded data must have a duty cycle between: - 48% and 52% in OOK, - 45% and 55% in FSK. MC33593 Freescale Semiconductor, Inc. The following example shows a complete message with Preamble, ID, Header words followed by 2 data bits, and an EOM. The preamble is placed at the beginning of both ID and Header words. Figure 5: Complete message example 1 1 0 0 1 0 0 0 0 1 1 0 1 0 Preamble MESSAGE PROTOCOL ID Preamble Header Data EOM Freescale Semiconductor, Inc... the sleep/run cycle period is equal to (SR+1) × TStrobe. If SOE=0, these timings constraints must be respected by the external control applied on pin STROBE. Figure 6: Complete telegram with ID detection P+ID P+ID P+ID P+ID P+ID P+ID P+Header Data EOM RF signal Run TStrobe Sleep SR × TStrobe ID detected Run Sleep P+ID = Preamble ID P+Header = Preamble Header Figure 7: Complete telegram with tone detection Tone Header Data EOM RF signal Run TStrobe Sleep SR × TStrobe ID detected Run Sleep Figures 8 & 9 detail RF signals and the processing done by the receiver in several configuations. Figure 8: Telegrams with ID DME=1, HE=1 Preamble ID Preamble ID ID detected Data DME=1, HE=0 Preamble ID ID ID ID ID ID ID ID ID ID ID ID ID ID Data EOM RF signal ID detected ID ID ID ID ID ID ID ID Data SPI output SPI output Preamble ID Preamble Header Data EOM RF signal © Motorola, Inc., 2002. MOTOROLA SEMICONDUCTORS PRODUCTS For More Information On This Product, 6 Go to: www.freescale.com revision 7.0, 5 February 2002 Non Disclosure Agreement Required If the receiver is continuously Sleep/Run cycling, the ID word has to be recognized to stay in Run mode. Consequently, the transmitted ID burst has to be long enough to include two consecutive receiver Run cycles. If the Strobe oscillator is enabled (SOE=1), the circuit is in Sleep mode during SR × TStrobe and in Run mode during TStrobe (where TStrobe is the Strobe oscillator period and SR is the Strobe Ratio, see Table 5). Therefore, MC33593 Freescale Semiconductor, Inc. Figure 9: Telegrams with tone DME=1, HE=1 Tone Tone detected Data DME=1, HE=0 Tone Tone detected Tone Data SPI output REC