Dual/Hex Low-Side Switch

www.DataSheet4U.com Freescale Semiconductor, Inc. Document order number: MC33397/D Rev 2.0, 03/2003 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control The 33397 is a low-side switch that is user configurable to be either two 333 mΩ outputs (dual mode) or six 900 mΩ outputs (hex mode). Each output is internally current limited and short-circuit protected. Output fault detection capability includes “off state” open loads and “on state” short-to-battery conditions. Faults for each output are latched into the fault register and serially shifted out during serial communication. 33397 DUAL/HEX LOW-SIDE SWITCH Freescale Semiconductor, Inc... Features • User Configurable to be Either Two 333 mΩ Outputs (Dual Mode) or Six 900 mΩ Outputs (Hex Mode) • Output Inductive Energy Clamps • Parallel Input (3.3 V and 5.0 V Compatible) or Serial Peripheral Interface (SPI) Control • 8-Bit SPI Control and Fault Diagnostics • Short-to-Battery Detection and Shutdown with Automatic Retry • OFF-State Open-Circuit Detection • Programmable Overvoltage Shutdown (VPWR Pin) • Undervoltage Shutdown (VDD Pin) • Sleep Mode—IDD ≤ 25 µA (1.0 µA Typical) DW SUFFIX PLASTIC PACKAGE CASE 751E 24-LEAD SOICW ORDERING INFORMATION Device MC33397DW/R2 Temperature Range (TA) -40 to 125°C Package 24 SOICW 33397 Simplified Application Diagram EN VDD 13 33397 VPWR 24 A0 23 A1 14 +VBAT Microcontroller with Bus EN 15 CS 10 SCLK 3 SI 4 CMOS Input Logic CMOS Serial Shift Registers and Latches Output Switches and Sense Circuits A2 12 A3 11 A4 2 SO 9 A5 1 GND 5-8, 17-20 This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc. 2003 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. CS SI SO SCLK A0 3.0 V + Sleep Mode 50 V 1.2 Ω ILIMIT Dual Mode 40 µA Logic 8-Bit SPI Interface + - 3.0 V Sleep Mode 40 µA Logic ILIMIT Dual Mode + 3.0 V Sleep Mode 40 µA 50 V 1.2 Ω ILIMIT 50 V 1.2 Ω A1 A4 3.0 V + Sleep Mode 50 V 1.2 Ω ILIMIT 40 µA Logic Dual Mode 3.0 V + Sleep Mode 50 V 1.2 Ω ILIMIT 40 µA Logic Logic Logic A2 Freescale Semiconductor, Inc... Dual Mode + - 3.0 V A3 Sleep Mode 40 µA 50 V 1.2 Ω ILIMIT A5 P0 10 µA Parallel Gate Control and Mode Control Logic 10 µs Filter Overvoltage Shutdown Low VDD Detect and POR Timer P1 10 µA 30 V + 3.0 V VDD VPWR P2 10 µA + 0.75 VDD 0.25 VDD + - SQ R VDD EN Figure 1. 33397 Simplified Block Diagram 33397 2 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. A5 A4 SCLK SI GND GND GND GND SO CS A3 A2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VPWR A0 P2 P1 GND GND GND GND P0 EN A1 VDD Freescale Semiconductor, Inc... PIN FUNCTION DESCRIPTION Pin 1, 2, 11, 12, 14, 23 3 4 5–8, 17–20 9 10 13 15 16 21 22 Pin Name A0–A5 SCLK SI GND SO CS VDD EN P0 P1 P2 Power outputs SPI clock input SPI serial input Power and signal ground SPI serial output SPI chip select Supply input pin Enable In hex mode, P0 controls output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously In hex mode, P1 controls output A1. In dual mode, P2 controls outputs A1, A2, and A3 simultaneously In hex mode, P2 controls output A2. P2 is also the mode control pin. If 0.25*VDD 0.8*VDD SO Enable Time (10 K Pull-Up Resistor on SO) CS=0.8 V to SO Low Impedance SO Rise Time CL < 200 pF SO Fall Time CL < 200 pF SO Valid Time Falling Edge of SCLK to SO Valid Required Time Between Falling Edge of CS to Rising Edge of SCLK Required TIme Between Rising Edge of CS to Falling Edge of SCLK Required Time Between SI to Rising Edge of SCLK POR/EN Wake-Up Timer Mode Change Timer (P2) tLEAD tLAG tSU tPOR tMODE tVALID – – – – 20 5.0 65 100 0 25 40 10 80 ns 140 ns 50 45 60 25 ns µs µs tSOFALL – 30 50 ns tSORISE – 30 50 ns tSOEN – 80 110 ns tSODIS – 80 110 ns ns MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33397 7 Freescale Semiconductor, Inc. Timing Diagrams CS tLEAD tLAG SCLK Freescale Semiconductor, Inc... SI tSU SO tSOEN tVALID tSODIS Figure 2. SPI Timing Diagram CS SCLK SI HIZ SO PO P1 P2 EN A0 tPON tFALL tRISE A1 A2 tPOFF A3-A5 Note: In hex mode, the outputs are controlled by the SPI or by the parallel inputs. However, P0, P1, and P2 only control A0, A1, and A2, respectively. When EN goes high, the part is disabled. Figure 3. Operation Waveforms for Hex Control 33397 8 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. VDD 0.8 VDD P0, P1 0V tPON tR tPOFF 0.2 VDD tF 80% Freescale Semiconductor, Inc... VDS 0V 20% Figure 4. Response Times Short-to-Battery Period VDD VIN (P0, P1) VDS ILIMIT ILOAD ILOAD