High Voltage Switching Regulator

MC33363B High Voltage Switching Regulator The MC33363B is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on−chip 700 V/1.0 A SENSEFETt power switch, 500 V active off−line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle−by−cycle current limiting, input undervoltage lockout with hysteresis, overvoltage protection, and thermal shutdown. This device is available in a 16−lead dual−in−line and wide body surface mount packages. Features http://onsemi.com MARKING DIAGRAMS 16 1 SO−16WB DW SUFFIX CASE 751N MC33363BDW AWLYYWWG • • • • • • • • • • On−Chip 700 V, 1.0 A SENSEFET Power Switch Rectified 240 Vac Line Source Operation On−Chip 500 V Active Off−Line Startup FET Latching PWM for Double Pulse Suppression Cycle−By−Cycle Current Limiting Input Undervoltage Lockout with Hysteresis Over−V oltage Protection Trimmed Internal Bandgap Reference Internal Thermal Shutdown Pb−Free Packages are Available* A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS www.DataSheet4U.com Startup Input 1 16 Power Switch Drain VCC AC Input Startup Input Regulator Output 8 6 RT CT Osc 7 PWM Latch S Q PWM R Ipk Thermal LEB Compensation 9 EA 10 Voltage Feedback Input Driver OVP Startup Reg UVLO VCC 3 Overvoltage Protection Input 11 16 Power Switch Drain DC Output 1 3 4 13 GND 5 12 11 10 9 (Top View) Overvoltage Protection Input Voltage Feedback Input Compensation GND RT Mirror CT Regulator Output 6 7 8 ORDERING INFORMATION Device MC33363BDW MC33363BDWG MC33363BDWR2 Package SO−16WB SO−16WB (Pb−Free) Shipping† 47 Units/Rail 47 Units/Rail SO−16WB 1000 Tape & Reel MC33363BDWR2G SO−16WB 1000 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. GND 4, 5, 12, 13 Figure 1. Simplified Application *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 1 November, 2005 − Rev. 6 Publication Order Number: MC33363B/D MC33363B MAXIMUM RATINGS (Note 1) Rating Power Switch (Pin 16) Drain Voltage Drain Current Startup Input Voltage (Pin 1, Note 2) Power Supply Voltage (Pin 3) Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Overvoltage Protection Input (Pin 11) RT (Pin 6) CT (Pin 7) Thermal Characteristics P Suffix, Dual−In−Line Case 648E Thermal Resistance, Junction−to−Air Thermal Resistance, Junction−to−Case DW Suffix, Surface Mount Case 751G Thermal Resistance, Junction−to−Air Thermal Resistance, Junction−to−Case Operating Junction Temperature Storage Temperature Symbol VDS IDS Vin VCC VIR Value 700 1.0 500 40 −1.0 to Vreg Unit V A V V V °C/W RqJA RqJC RqJA RqJC TJ Tstg 80 15 95 15 −25 to +150 −55 to +150 °C °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015. Machine Model Method 200 V. 2. Maximum power dissipation limits must be observed. Thigh = +125°C 3. Tested junction temperature range for the MC33363B: Tlow = −25°C ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.) Characteristic REGULATOR (Pin 8) Output Voltage (IO = 0 mA, TJ = 25°C) Line Regulation (VCC = 20 V to 40 V) Load Regulation (IO = 0 mA to 10 mA) Total Output Variation over Line, Load, and Temperature OSCILLATOR (Pin 7) Frequency CT = 390 pF TJ = 25°C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) CT = 2.0 nF TJ = 25°C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) Frequency Change with Voltage (VCC = 20 V to 40 V) ERROR AMPLIFIER (Pins 9, 10) Voltage Feedback Input Threshold Line Regulation (VCC = 20 V to 40 V, TJ = 25°C) Input Bias Current (VFB = 2.6 V, TJ = 0 − 125°C) Open Loop Voltage Gain (TJ = 25°C) Gain Bandwidth Product (f = 100 kHz, TJ = 25°C) Output Voltage Swing High State (ISource = 100 mA, VFB < 2.0 V) Low State (ISink = 100 mA, VFB > 3.0 V) VFB Regline IIB AVOL GBW VOH VOL 2.52 − − 70 0.85 4.0 − 2.6 0.6 20 82 1.0 5.3 0.2 2.68 5.0 500 94 1.15 − 0.35 V mV nA dB MHz V fOSC 260 255 60 59 DfOSC/DV − 285 − 67.5 − 0.1 310 315 75 76 2.0 kHz kHz Vreg Regline Regload Vreg 5.5 − − 5.3 6.5 30 44 − 7.5 500 200 8.0 V mV mV V Symbol Min Typ Max Unit http://onsemi.com 2 MC33363B ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.) Characteristic OVERVOLTAGE DETECTION (Pin 11) Input Threshold Voltage Input Bias Current (Vin = 2.6 V, TJ = −25 − 125°C) PWM COMPARATOR (Pins 7, 9) Duty Cycle Maximum (VFB = 0 V) Minimum (VFB = 2.7 V) POWER SWITCH (Pin 16) Drain−Source On−State Resistance (ID = 200 mA) TJ = 25°C TJ = Tlow to Thigh Drain−Source Off−State Leakage Current (VDS = 650 V) TJ = 25°C TJ = Tlow to Thigh Rise Time Fall Time OVERCURRENT COMPARATOR (Pin 16) Current Limit Threshold (RT = 10 k) STARTUP CONTROL (Pin 1) Peak Startup Current (Vin = 50 V) (TJ = −25 − 100°C) VCC = 0 V VCC = (Vth(on) − 0.2 V) Off−State Leakage Current (Vin = 50 V, VCC = 20 V) UNDERVOLTAGE LOCKOUT (Pin 3) Startup Threshold (VCC Increasing) Minimum Operating Voltage After Turn−On TOTAL DEVICE (Pin 3) Power Supply Current Startup (VCC = 10 V, Pin 1 Open) Operating THERMAL SHUTDOWN Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) 4. Tested junction temperature range for the MC33363B: Tlow = −25°C Tsd TH Thigh = +125°C − − 135 30 − − °C ICC − − 0.25 3.2 0.5 5.0 mA Vth(on) VCC(min) 11 7.5 15.2 9.5 18 11.5 V V Istart 2.0 2.0 ID(off) − 5.0 5.0 40 8.0 8.0 200 mA mA Ilim 0.5 0.72 0.9 A RDS(on) − − ID(off) − − tr tf − − 0.25 − 50 50 1.0 50 − − ns ns 15 − 17 39 mA W % DC(max) DC(min) 48 − 50 0 52 0 Vth IIB 2.47 − 2.6 100 2.73 500 V nA Symbol Min Typ Max Unit http://onsemi.com 3 MC33363B I PK, POWER SWITCH PEAK DRAIN CURRENT (A 1.0 M f OSC , OSCILLATOR FREQUENCY (Hz) CT = 100 pF 500 k C = 200 pF T 200 k CT = 500 pF 100 k CT = 1.0 nF 50 k 20 k CT = 2.0 nF VCC = 20 V TA = 25°C 1.0 0.8 0.6 0.4 0.3 0.2 0.15 0.1 7.0 Inductor supply voltage and inductance value are adjusted so that Ipk turn−off is achieved at 5.0 ms. 10 15 20 30 40 VCC = 20 V CT = 1.0 mF TA = 25°C CT = 5.0 nF CT = 10 nF 10 k 7.0 10 15 20 30 50 70 50 70 RT, TIMING RESISTOR (kW) RT, TIMING RESISTOR (kW) Figure 2. Oscillator Frequency versus Timing Resistor Figure 3. Power Switch Peak Drain Current versus Timing Resistor 0.8 I chg /I dscg , OSCILLATOR CHARGE/DISCHARGE CURRENT (mA) 0.5 VCC = 20 V TA = 25°C Dmax, MAXIMUM OUTPUT DUTY CYCLE (%) 70 RD/RT Ratio Discharge Resistor Pin 7 to GND VCC = 20 V CT = 2.0 nF TA = 25°C 60 0.3 0.2 0.15 0.1 0.08 7.0 10 15 20 30 50 70 50 40 30 1.0 RC/RT Ratio Charge Resistor Pin 7 to Vreg 2.0 3.0 5.0 7.0 10 TIMING RESISTOR RATIO RT, TIMING RESISTOR (kW) Figure 4. Oscillator Charge/Discharge Current versus Timing Resistor Figure 5. Maximum Output Duty Cycle versus Timing Resistor Ratio θ, EXCESS PHASE (DEGREES) 80 Gain 60 Phase 40 20 0 VCC = 20 V VO = 1.0 to 4.0 V RL = 5.0 MW CL = 2.0 pF TA = 25°C Vsat , OUTPUT SATURATION VOLTAGE (V) A VOL, OPEN LOOP VOLTAGE GAIN (dB) 100 0 30 60 90 0 Source Saturation (Load to Ground) Vref −1.0 − 2.0 120 150 180 10 M 2.0 1.0 Sink Saturation (Load to Vref) GND VCC = 20 V TA = 25°C −20 10 100 1.0 k 10 k 100 k 1.0 M 0 0 0.2 0.4 0.6 0.8 1.0 f, FREQUENCY (Hz) IO, OUTPUT LOAD CURRENT (mA) Figure 6. Error Amp Open Loop Gain and Phase versus Frequency Figure 7. Error Amp Output Saturation Voltage versus Load Current http://onsemi.com 4 MC33363B VCC = 20 V AV = −1.0 CL = 10 pF TA = 25°C 20 mV/DIV VCC = 20 V AV = −1.0 CL = 10 pF TA = 25°C 0.5 V/DIV 1.0 ms/DIV 1.80 V 3.00 V 1.75 V 1.75 V 1.70 V 0.50 V 1.0 ms/DIV Figure 8. Error Amplifier Small Signal Transient Response Figure 9. Error Amplifier Large Signal Transient Response Δ V reg, REGULATOR VOLTAGE CHANGE (mV) 0 I pk , PEAK STARTUP CURRENT (mA) VCC = 20 V RT = 10 k CPin 8 = 1.0 mF TA = 25°C 6 5 4 3 2 1 0 VPin 1 = 50 V TA = 25°C −20 −40 −60 −80 0 4.0 8.0 12 16 20 0 2.0 4.0 6.0 8.0 10 12 Ireg, REGULATOR SOURCE CURRENT (mA) VCC, POWER SUPPLY VOLTAGE (V) Figure 10. Regulator Output Voltage Change versus Source Current Figure 11. Peak Startup Current versus Power Supply Voltage R DS(on), DRAIN−SOURCE ON−RESISTANCE (Ω ) 32 ID = 200 mA COSS, DRAIN−SOURCE CAPACITANCE (pF) 160 VCC = 20 V TA = 25°C 24 120 16 80 8.0 Pulse tested at 5.0 ms with < 1.0% duty cycle so that TJ is as close to TA as possible. 0 −50 −25 0 25 50 75 100 125 150 40 COSS measured at 1.0 MHz with 50 mVpp. 10 100 1000 VDS, DRAIN−SOURCE VOLTAGE (V) 0 1.0 TA, AMBIENT TEMPERATURE (°C) Fig