Dual High-Side TMOS Driver

www.DataSheet4U.com Freescale Semiconductor Advance Information Document Number: MC33285 Rev. 5.0, 2/2007 Dual High-Side TMOS Driver A single input controls the 33285 in driving two external high-side NChannel TMOS power FETs controlling incandescent or inductive loads. Pulse Width Modulated (PWM) input control to 1.0 kHz is possible. The 33285 contains a common internal charge pump used to enhance the Gate voltage of both FETs. An external charge capacitor provides access to the charge pump output. Both external FETs are protected against inductive load transients by separate internal source-to-gate dynamic clamps. The power FETs are protected by the 33285 with short-circuit delay time of 800 µs. The device is designed to withstand reverse polarity battery and load dump transients, encountered in automotive applications. Features • PWM Capability • Power TMOS Number One (OUT1) Short-Circuit Detection and Short-Circuit Protection • Voltage Range 7.0 V ≤ 40 V • Extended Temperature Range from -40°C ≤ 125°C • Load Dump Protected • Overvoltage Detection and Activation of OUT2 During Overvoltage • Single Input Control for Both Output Stages • Capacitor Value of 100 nF Connected to Pin CP • Analog Input Control Measurement Detection • OUT1 LOAD Leakage Measurement Detection • Pb-Free Packaging Designated by Suffix Code EF 33285 HIGH-SIDE TMOS DRIVER D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN ORDERING INFORMATION Device MC33285D/R2 MCZ33285EF/R2 Temperature Range (TA) -40°C to 125°C Package 8 SOICN VCC 33285 VCC CP OUT2 DRN VPWR Input Control IN GND OUT1 SRC Motor Figure 1. 33285 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VIGN Kl.30 CP VCC CCP + VREF R S Oscillator and Divider Charge Pump DRN Bandgap Rthr ION2 ION1 tLDDET Load Dump Detection IN THRIN2 OUT2 tOUT2ECT VOUT2-VDRN> VTH2 RQ S IOUTN2 VOUT1-VSRC> VTH1 + + OUT2 Activation Time OUT1 THRIN1 GND OC Detection IOUTN1 M + - RQ S tOCDET Start tOCDET SCPC SRC Figure 2. 33285 Simplified Internal Block and Typical Applications Diagram 33285 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS SRC OUT1 DRN OUT2 11 88 77 66 5 5 IN GND VCC CP 22 33 44 Figure 3. 33285 Pin Connections Table 1. 33285 Pin Definitions Pin Number 1 2 3 4 5 6 7 8 Pin Name SRC Formal Name Source Output 1 Drain Output 2 Charge Pump Voltage Power Supply Ground Input Definition OUT2 external FET Source connection This pin is output number 1 OUT1 and OUT2 external FET Drain connection This pin is output number 2 External capacitor connection for internal the Charge Pump Battery supply voltage This is the ground pin. Voltage level sensitive input for OUT1 and OUT2 OUT1 DRN OUT2 CP VCC GND IN 33285 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS Maximum Voltage at Pins OUT1 and OUT2 Maximum Voltage at Pin CP Input Voltage VI at DRN Input Voltage VI at SRC Input Voltage at Pin VCC Input Voltage at Pin IN. Condition: -2.0 V < VVCC < 40 V Operational Voltage VVCC at Pin VCC THERMAL RATINGS Storage Temperature Operating Ambient Temperature Peak Package Reflow Temperature During Reflow (1), (2) VOUT VCP VDRN VSRC VCC VIN VVCC VVCC + 20 50 -2.0 to 40 -5.0 to 40 -2.0 to 40 -2.0 to VVCC 7.0 to VI V V V V V Symbol Value Unit V V TSTG TA TPPRT -40 to150 -40 to 125 Note 2 °C °C °C Notes 1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33285 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic OVERVOLTAGE AND OVER CURRENT Load Dump Activation Time Error Voltage Threshold SRC PIN 1 Leakage Current Leakage Current Detection Time DRN PIN 3 Operating Current (7.0 V < VDRN < 20 V) Leakage Current (0 V < VDRN < 20 V, VVCC < 4.0 V) OUT1, PIN 2, AND OUT2 PIN 4 Output ON Voltage. Charge Pump ON Turn OFF Current, VOUT > 0.5 V VCC PIN 6 Supply Voltage Range Quiescent Supply Current at VCC = 20 V IN PIN 8 Input Low Voltage OUT1 Input High Voltage OUT1 Input Hysteresis OUT1 and OUT2 Input Pull Down Current, 0.7 V < VIN < 6.0 V Open Input Voltage Input Low Voltage OUT2 Input High Voltage OUT2 VIL VIH VHYS IIN VIOP VIL2 VIH2 — 1.7 0.4 7.5 — — 3.9 — — — 15 — — — 0.7 — — 16.5 0.7 3.0 — V V V µA V V V VCC ICC 7.0 — — — 40 10 V mA VON IOUTOFF — 66 — 110 VCC + 15 154 V µA IDRN ILEAK-DRN — -5.0 — — 1.5 5.0 mA µA ILCDET tLCDET 15 130 30 200 50 270 mA µA Symbol Min Typ Max Unit tOUT2ACT VDRN - VSRC 300 1.12 460 — 620 1.44 ms V 33285 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic OVER VOLTAGE AND OVER CURRENT Load Dump Detection Time Over Current Detection Time OUT1 PIN 2, AND OUT2 PIN 4 Turn ON Time, OUT1: 8.0 nF, 10 µA; OUT2:16 nF, 10 µA -7.0 V < VCC < 10 V, VOUT > VCC + 7.0 -10 V < VCC < 20 V, VOUT > VCC + 11 tON — — — — 1.5 1.5 ms tLDDET tOCDET 250 520 400 800 550 1080 µs µs Symbol Min Typ Max Unit 33285 6 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The power FETs are turned ON by charging their gate capacities with a current flowing out of pins OUT1 and OUT2. During PWM, the values of table below are guaranteed. They are measured with 8.0 nF on OUT1 and 16 nF on OUT2. Test condition VIN: ramp 0 V ≤ 2.5 V or 2.5 V ≤ 5.0 V. IN 5.0 V 2.5 V IN THRIN2 THRIN1 VOUT1 VVCC + 7.0 VCCP VOUT2 VOUT2 20 ms 5.0 V 2.5 V IN 0V VOUT1MAX IN 2.5 V VOUT2MAX VOUT2 VOUT1 0V 0V tON1 tON2 0 tON3 0 tON1 tON3 tON2 VOLTAGE VVCC 7.0 V < VVCC < 10 V 10 V < VVCC < 20 V 20 V < VVCC < 40 V MINIMUM VOUT1, OUT2 AFTER TON1 = 100 µSEC VVCC - 0.7 V VVCC - 0.7 V VVCC - 0.7 V MINIMUM VOUT1,OUT2 AFTER TON2 = 1.0 µSEC VVCC + 5.95 V VVCC + 9.35 V MINIMUM VOUT1,OUT2 AFTER TON3 = 1.5 µSEC VVCC + 7.0 V VVCC + 11 V Figure 4. Turn On Behavior Turn Off Characteristics The output voltages at OUT1 and OUT2 are limited by The power FETs on OUT1 and OUT2 are turned OFF by controlling the current sources ION1, ION2 to avoid current discharging the gate capacity with the constant discharge flowing through the external or the internal zener diode. current IOUTOFF. When voltage power supply plus threshold voltage • Discharge current IOUTxOFF is IOUTxOFF = 110 µA (VCC + VTH) is reached, the current sources are turned OFF. condition: VOUT x > 0.5 V ( VIN < VTHRxIN ) • Threshold VTH1 for OUT1 output voltage control is 7.0 V < VTH1 < VZ • Test conditions for switching OFF the power FETs: • Threshold VTH2 for OUT2 output voltage control is 1. IN open 7.0 V < VTH2 < 15 V 2. Stages disabled via pin IN 3. Stage OUT1 disabled by an over current error 33285 Analog Integrated Circuit Device Data Freescale Semiconductor 7 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTRODUCTION The 33285 contains only one charge pump for two outputs.The outputs, OUT1 and OUT2, are switched ON and OFF by the input (IN) .There are three ways to control the outputs: OUT1 can be switched alone OUT1 and OUT2 can be switched together OUT2 can be switched when OUT1 is already on In the last case, the voltage drop on OUT1 when charging OUT2 is limited. The external capacitor (CCP) connected to the CHARGE PUMP (CP) pin is used to store the charge continuously delivered by the charge pump. The voltage on this pin is limited to a maximum value VCPMAX. Both outputs are sourced with a constant current from CCP to switch them ON. Additionally, the gates of the power FETs are precharged from voltage power supply (VCC) to prevent CCP from being discharged by a voltage on OUT1 or OUT2, is still lower than VVCC. The values of the output voltages are limited to VOUT1MAX and VOUT2MAX. The power FET on OUT1 is protected against an exceeded gate-source voltage by an internal zener diode. Channel One protects the N-Channel power FET on OUT1 undercurrent and short-circuit conditions. The drain-source voltage of the FET on OUT1 is checked if Channel One is switched ON. The internal error voltage threshold determines the maximum drain-source voltage allowing the power FET to stay in the ON state. If the measured drain-source volt