8-Bit Bus-Compatible Latches

MC14598B 8−Bit Bus−Compatible Latches The MC14598B is an 8−bit latch addressed with an external binary address. The 8 latch−outputs are high drive, three−state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. Features http://onsemi.com PDIP−18 P SUFFIX CASE 707 1 • • • • • • • • • Serial Data Input Three−State Bus Compatible Parallel Outputs Three−State Control Pin (Enable) TTL Compatible Input Open Drain Full Flag (Multiple Latch Wire−O Ring) Master Reset Level Shifting Inputs on All Except Enable Diode Protection — All Inputs Supply Voltage Range — 3.0 Vdc to 18 Vdc Capable of Driving TTL Over Rated Temperature Range With www.DataSheet4U.com Fanout as Follows: 1 TTL Load 4 LSTTL Loads • Pb−Free Package is Available* MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter DC Supply Voltage Range Input Voltage Range, enable (DC or Transient) Input Voltage Range, all Other Inputs (DC or Transient) Output Voltage Range, (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8−Second Soldering) Symbol VDD Vin Vin Vout Iin, Iout PD TA Tstg TL Value −0.5 to +18.0 −0.5 to VDD +0.5 −0.5 to VDD +12 −0.5 to VDD +0.5 ±10 500 −55 to +125 −65 to +150 260 Unit V V V V mA mW °C °C °C MARKING DIAGRAM 18 MC14598BCP AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package OUTPUT TRUTH TABLE Enable 1 0 Outputs High Impedance Dn Dn = State of nth latch NC = NO CONNECTION ORDERING INFORMATION Device MC14598BCP MC14598BCPG Package PDIP−18 PDIP−18 (Pb−Free) Shipping 20 Units/Rail 20 Units/Rail Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Publication Order Number: MC14598B/D 1 June, 2006 − Rev. 6 MC14598B PIN ASSIGNMENT D0 RESET DATA ENABLE NC STROBE A0 A1 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD D1 D2 D3 D4 D5 D6 D7 A2 RESET DATA STROBE A0 A1 A2 7 8 ADDRESS 10 DECODER VDD = 18 VSS = 9 2 3 6 8 LATCHES BLOCK DIAGRAM ENABLE 4 1 17 16 15 14 13 12 11 D0 D1 D2 D3 D4 D5 D6 D7 THREE STATE OUTPUT BUFFERS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Input Voltage Other Inputs (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (Full — Sink Only) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current 3−State Leakage Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) “0” Level VIL 5.0 10 15 “1” Level VIH 5.0 10 15 − − − 3.5 7.0 11 1.5 3.0 4.0 – − − – − − 3.5 7.0 11 2.25 4.50 6.75 2.75 5.50 8.25 1.5 3.0 4.0 – − − – − − 3.5 7.0 11 1.5 3.0 4.0 – − − Vdc VIH 5.0 10 15 2.0 6.0 10 − − − 2.0 6.0 10 1.9 3.1 4.3 – − − 2.0 6.0 10 – − − Vdc − 55_C 25_C 125_C Characteristic Symbol VOL Min − − − Max Min – − − Typ (Note 2) 0 0 0 Max Min – − − Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 – − − 0.8 1.6 2.4 0.05 0.05 0.05 – − − 0.8 1.6 2.4 0.05 0.05 0.05 – − − 0.8 1.6 2.4 Vdc “1” Level Vin = 0 or VDD Input Voltage (Note 3), Enable (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL − − − − − − 1.1 2.2 3.4 – − − VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Source IOH 5.0 10 15 Sink IOL 5.0 10 15 15 15 − 5.0 10 15 5.0 10 –1.0 − − 1.6 − − − − − − − − – − − − − − ± 0.1 ± 0.1 − 5.0 10 20 –1.0 − − 1.6 − − − − − − − − –2.0 –6.0 –12 3.2 6.0 12 ± 0.00001 ± 0.00001 5.0 0.005 0.010 0.015 – − − – − − ± 0.1 ± 0.1 7.5 5.0 10 20 –1.0 − − 1.6 − − − − − – − − – − − – − − ± 1.0 ± 3.0 − 150 300 600 mAdc mAdc Iin ITL Cin IDD mAdc mAdc pF mAdc Total Supply Current at an External Load Capacitance of 130 pF (Note 3) IT IT = (2.0 mA/kHz) f + IDD IT = (4.0 mA/kHz) f + IDD IT = (6.0 mA/kHz) f + IDD mAdc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. http://onsemi.com 2 MC14598B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 4) (TA = 25_C, CL = 130 pF + 1 TTL Load) VDD Vdc 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 tWH, tWL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tsu 5.0 10 15 5.0 10 15 th 5.0 10 15 5.0 10 15 trem 5.0 10 15 100 50 35 100 50 35 20 20 20 50 25 20 50 25 20 – 25 – 15 – 10 − − − − − − − − − ns 100 50 35 200 100 70 50 25 20 100 50 35 − − − − − − ns 320 240 160 200 100 80 200 100 80 300 160 100 160 120 80 100 50 40 100 50 40 150 80 50 − − − − − − − − − − − − ns − − − − − − − − − 160 125 100 200 100 80 175 90 70 320 250 200 400 200 160 350 180 140 ns All Types Typ (Note 5) 100 50 40 Characteristic Symbol Min − − − Max 200 100 80 ns Unit ns Output Rise and Fall Time tTLH, tTHL = (0.5 ns/pF) CL + 35 ns tTLH, tTHL = (0.2 ns/pF) CL + 25 ns tTLH, tTHL = (0.16 ns/pF) CL + 20 ns Propagation Delay Time Enable to Output tTLH, tTHL Strobe to Output Reset to Output Pulse Width Enable Strobe Increment Reset Setup Time Data Address Hold Time Data Address Reset Removal Time 4. The formulas given are for the typical characteristics only at 25_C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 3 MC14598B MC14598B FUNCTION DIAGRAM RESET DATA 2 3 TO OTHER LATCHES STROBE ENABLE 6 4 TO OTHER LATCHES A0 A1 7 8 ADDRESS DECODER ADDITIONAL 7 LATCHES ZERO SELECT 1 D0 VDD EACH LATCH VSS A2 10 (M.S.B) 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 MC14598B TIMING DIAGRAM 90% 10% 50% tTHL D7 tPLH RESET A0, A1, A2 DATA STROBE ENABLE * 1 50% tPLH tTLH 90% 10% 20 ns 50% tsu tsu 50% th th 90% 10% tPHL tW 90% 10% 20 ns 90% 10% 20 ns tW tW *1.4 V with VDD = 5.0 V NOTES: 1. High−impedance output state (another device controls bus). 2. Output Load as for MC14597B. http://onsemi.com 4 MC14598B LATCH TRUTH TABLE Strobe 0 1 X Reset 1 1 0 Address Latch * Data 0 Other Latches * * 0 X X X X = Don’t care Increment TRUTH TABLE FOR MC14597B Enable X X 1 0 1 Reset 1 1 0 1 1 Address Counter Count Up No Change Reset to Zero No Change If at ADDRESS 7 Full − − Set to One Set to One To Zero on Falling Edge of STROBE *= No change in state of latch X = Don’t care TEST LOAD, ALL OUTPUTS +5.0 V RL = 2.5 k Dn 130 pF 11.7 k Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed to be reliable. Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under the patent rights of Motorola or others. The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time. http://onsemi.com 5 MC14598B PACKAGE DIMENSIONS PDIP−18 CASE 707−02 ISSUE D J 18 1 10 B 9 L NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15 _ 0.51 1.02 A C M DIM A B C D F G H J K L