(MC14555B / MC14556B) Dual Binary to 1-of-4 Decoder/Demultiplexer

MC14555B, MC14556B Dual Binary to 1−of−4 Decoder/Demultiplexer The MC14555B and MC14556B are constructed with complementary MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer has two select inputs (A and B), an active low Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the selected output go to the “high” state, and the MC14556B has the selected output go to the “low” state. Expanded decoding such as binary−to−hexadecimal (1−of−16), etc., can be achieved by using other MC14555B or MC14556B devices. Applications include code conversion, address decoding, memory selection control, and demultiplexing (using the Enable input as a data input) in digital data transmission systems. Features 1 SOIC−16 D SUFFIX CASE 751B 1 16 1455xBG AWLYWW 1 http://onsemi.com MARKING DIAGRAMS 16 MC1455xBCP AWLYYWWG 1 PDIP−16 P SUFFIX CASE 648 • • • • • • Diode Protection on All Inputs Active High or Active Low Outputs Expandable Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Pb−Free Packages are Available* www.DataSheet4U.com MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8−Second Soldering) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Value −0.5 to +18.0 −0.5 to VDD + 0.5 ± 10 500 −55 to +125 −65 to +150 260 Unit V V mA SOEIAJ−16 F SUFFIX CASE 966 1 x A WL, L YY, Y WW, W G 16 MC1455xB ALYWG 1 = 5 or 6 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENTS mW °C °C °C MC14555B EA AA BA Q0A Q1A Q2A Q3A VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD EB AB BB Q0B Q1B Q2B Q3B EA AA BA Q0A Q1A Q2A Q3A VSS MC14556B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD EB AB BB Q0B Q1B Q2B Q3B Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C To 125°C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 1 June, 2006 − Rev. 8 Publication Order Number: MC14555B/D MC14555B, MC14556B TRUTH TABLE Inputs Enable E 0 0 0 0 1 Select B 0 0 1 1 X A 0 1 0 1 X 0 0 0 1 0 Outputs MC14555B 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 MC14556B 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 BLOCK DIAGRAM MC14555B 2 3 1 A B E Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 4 5 6 7 12 11 10 9 VDD = PIN 16 VSS = PIN 8 2 3 1 MC14556B A B E Q0 Q1 Q2 Q3 4 5 6 7 12 11 10 9 X = Don’t Care 14 13 15 A B E 14 13 15 A B E Q0 Q1 Q2 Q3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55°C VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 − 5.0 10 15 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 0.64 1.6 4.2 − − − − − − − − − − − − ± 0.1 − 5.0 10 20 – 2.4 – 0.51 – 1.3 – 3.4 0.51 1.3 3.4 − − − − − – 4.2 – 0.88 – 2.25 – 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 − − − − − − − ± 0.1 7.5 5.0 10 20 – 1.7 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 − − − − − − − − − − − − ± 1.0 − 150 300 600 mAdc 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − mAdc 25°C 125°C Characteristic Symbol VOL Min − − − 4.95 9.95 14.95 − − − Max Min − − − 4.95 9.95 14.95 − − − Typ (Note 2) 0 0 0 5.0 10 15 2.25 4.50 6.75 Max Min − − − 4.95 9.95 14.95 − − − Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 − − − 1.5 3.0 4.0 0.05 0.05 0.05 − − − 1.5 3.0 4.0 0.05 0.05 0.05 − − − 1.5 3.0 4.0 Vdc “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance, (Vin = 0) Quiescent Current (Per Package) VIL VOH Vdc Vdc Sink Iin Cin IDD mAdc pF mAdc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT IT = (0.85 mA/kHz) f + IDD IT = (1.70 mA/kHz) f + IDD IT = (2.60 mA/kHz) f + IDD mAdc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25°C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 2 MC14555B, MC14556B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C) Characteristic Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 Min − − − − − − − − − Typ (Note 6) 100 50 40 220 95 70 200 85 65 Max 200 100 80 440 190 140 ns 400 170 130 Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time − A, B to Output tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 62 ns tPLH, tPHL = (0.5 ns/pF) CL + 45 ns Propagation Delay Time − E to Output tPLH, tPHL = (1.7 ns/pF) CL + 115 ns tPLH, tPHL = (0.66 ns/pF) CL + 52 ns tPLH, tPHL = (0.5 ns/pF) CL + 40 ns tPLH, tPHL ns tPLH, tPHL 5. The formulas given are for the typical characteristics only at 25°C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. INPUT E LOW 20 ns 20 ns 90% 50% 10% VDD VSS VDD VSS VOH VOL 20 ns INPUT B tPHL OUTPUT Q3 MC14556B INPUT A HIGH, INPUT E LOW 20 ns 90% 50% 10% 90% 50% 10% 90% 50% 10% tTLH VDD tPLH VSS VOH A INPUTS (50% DUTY CYCLE) B INPUTS (50% DUTY CYCLE) OUTPUT Q1 All 8 outputs connect to respective CL loads. f in respect to a system clock. 1 2f tPLH OUTPUT Q3 MC14555B tTHL tPHL V tTLH OL VOH VOL tTHL Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms LOGIC DIAGRAM (1/2 of Dual) * A * B * E * *Eliminated for MC14555B Q3 Q2 Q1 Q0 http://onsemi.com 3 MC14555B, MC14556B ORDERING INFORMATION Device MC14555BCP MC14555BCPG MC14555BD MC14555BDG MC14555BDR2 MC14555BDR2G MC14555BFEL MC14555BFELG MC14556BCP MC14556BCPG MC14556BD MC14556BDR2 MC14556BDR2G MC14556BF MC14556BFEL MC14556BFELG Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOEIAJ−16 SOEIAJ−16 (Pb−Free) PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 SOIC−16 (Pb−Free) SOEIAJ−16 SOEIAJ−16 SOEIAJ−16 (Pb−Free) 2000 / Tape & Reel 2500 / Tape & Reel 50 Units / Tube 25 Units / Rail 48 Units / Rail 2000 / Tape & Reel 2500 / Tape & Reel 48 Units / Rail 25 Units / Rail Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC14555B, MC14556B PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE T −A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B 1 8 F S C L −T− H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC−16 CASE 751B−05 ISSUE J −A− 16 9 −B− 1 8 P 8 PL 0.25 (0.010) M B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1