(MC14555B / MC14556B) Dual Binary to 1-of-4 Decoder/Demultiplexer

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Binary to 1-of-4 Decoder/Demultiplexer The MC14555B and MC14556B are constructed with complementary MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer has two select inputs (A and B), an active low Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the selected output go to the “high” state, and the MC14556B has the selected output go to the “low” state. Expanded decoding such as binary–to–hexadecimal (1–of–16), etc., can be achieved by using other MC14555B or MC14556B devices. Applications include code conversion, address decoding, memory selection control, and demultiplexing (using the Enable input as a data input) in digital data transmission systems. • • • • • • Diode Protection on All Inputs Active High or Active Low Outputs Expandable Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Low–Power TTL Loads or One Low–Power Schottky TTL Load Over the Rated Temperature Range MC14555B MC14556B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit V V – 0.5 to + 18.0 www.DataSheet4U.com TA = – 55° to 125°C for all packages. TRUTH TABLE Inputs Enable E 0 0 0 0 1 Select B 0 0 1 1 X A 0 1 0 1 X 0 0 0 1 0 Outputs MC14555B 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 MC14556B 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 ± 10 500 – 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package† Storage Temperature Lead Temperature (8–Second Soldering) mA mW _C _C X = Don’t Care * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: “P and D/DW” Packages: – 7.0 mW/C From 65_ C To 125_ C Ceramic “L” Packages: – 12 mW/_ C From 100_ C To 125_ C BLOCK DIAGRAM MC14555B 2 3 1 A B E Q0 Q1 Q2 Q3 4 5 6 7 2 3 1 MC14556B A B E Q0 Q1 Q2 Q3 4 5 6 7 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v 14 13 15 A B E Q0 Q1 Q2 Q3 12 11 10 9 VDD = PIN 16 VSS = PIN 8 14 13 15 A B E Q0 Q1 Q2 Q3 12 11 10 9 REV 3 1/94 ©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14555B MC14556B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 — 5.0 10 15 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 0.64 1.6 4.2 — — — — — — — — — — — — ± 0.1 — 5.0 10 20 – 2.4 – 0.51 – 1.3 – 3.4 0.51 1.3 3.4 — — — — — – 4.2 – 0.88 – 2.25 – 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 — — — — — — — ± 0.1 7.5 5.0 10 20 – 1.7 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 — — — — — — — — — — — — ± 1.0 — 150 300 600 mAdc 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — mAdc Min — — — – 55_ C 25_ C 125_ C Max Min — — — Typ # 0 0 0 Max Min — — — Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 Vdc “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL — — — — — — 2.25 4.50 6.75 — — — VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.85 µA/kHz) f + IDD IT = (1.70 µA/kHz) f + IDD IT = (2.60 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_ C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. PIN ASSIGNMENTS MC14555B EA AA BA Q0A Q1A Q2A Q3A VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD EB AB BB Q0B Q1B Q2B Q3B EA AA BA Q0A Q1A Q2A Q3A VSS MC14556B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD EB AB BB Q0B Q1B Q2B Q3B MC14555B MC14556B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_ C) Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time — A, B to Output tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 62 ns tPLH, tPHL = (0.5 ns/pF) CL + 45 ns Propagation Delay Time — E to Output tPLH, tPHL = (1.7 ns/pF) CL + 115 ns tPLH, tPHL = (0.66 ns/pF) CL + 52 ns tPLH, tPHL = (0.5 ns/pF) CL + 40 ns Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 Min — — — — — — — — — Typ # 100 50 40 220 95 70 200 85 65 Max 200 100 80 440 190 140 ns 400 170 130 Unit ns tPLH, tPHL ns tPLH, tPHL * The formulas given are for the typical characteristics only at 25_ C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. INPUT E LOW 20 ns 20 ns 90% 50% 10% VDD VSS VDD VSS VOH VOL 20 ns INPUT B tPHL OUTPUT Q3 MC14556B tTHL tPLH OUTPUT Q3 MC14555B tTLH 90% 50% 10% INPUT A HIGH, INPUT E LOW 20 ns 90% 50% 10% tPLH VDD VSS VOH A INPUTS (50% DUTY CYCLE) 1 2f B INPUTS (50% DUTY CYCLE) OUTPUT Q1 All 8 outputs connect to respective CL loads. f in respect to a system clock. 90% 50% 10% V tTLH OL tPHL VOH VOL tTHL Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms LOGIC DIAGRAM (1/2 of Dual) * A * B * E * * Eliminated for MC14555B Q3 Q2 Q1 Q0 MOTOROLA CMOS LOGIC DATA MC14555B MC14556B 3 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 –B– 1 8 C L –T– SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L –T– H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MC14555B MC14556B 4 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7 _ 0.229 0.244 0.010 0.019 16 9 –B– 1 8 P 8 PL 0.25 (0.010) M B S G F K C –T– SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G