(MC14549B / MC14559B) Successive Approximation Registers

MC14549B, MC14559B Successive Approximation Registers The MC14549B and MC14559B successive approximation registers are 8−bit registers providing all the digital control and storage necessary for successive approximation analog−to−digital conversion systems. These parts differ in only one control input. The Master Reset (MR) on the MC14549B is required in the cascaded mode when more than 8 bits are desired. The Feed Forward (FF) of the MC14559B is used for register shortening where End−of−Conversion (EOC) is required after less than eight cycles. Applications for the MC14549B and MC14559B include analog−to−digital conversion, with serial and parallel outputs. Features http://onsemi.com MARKING DIAGRAMS 16 MC145x9BCP AWLYYWWG 1 PDIP−16 P SUFFIX CASE 648 1 • • • • • • • • • • • Totally Synchronous Operation All Outputs Buffered Single Supply Operation Serial Output Retriggerable Compatible with a Variety of Digital and Analog Systems such as the MC1408 8−Bit D/A Converter All Control Inputs Positive−Edge Triggered Supply Voltage Range = 3.0 Vdc to 18 Vdc www.DataSheet4U.com Capable of Driving 2 Low−Power TTL Loads, 1 Low−Power Schottky TTL Load or 2 HTL Loads Over the Rated Temperature Range Chip Complexity: 488 FETs or 122 Equivalent Gates Pb−Free Packages are Available* 16 SO−16W DW SUFFIX CASE 751G 1 MC145x9B AWLYYWWG 1 x A WL YY WW G = = = = = = 4 or 5 Assembly Location Wafer Lot Year Work Week Pb−Free Package MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter DC Supply Voltage Range Input Voltage Range, All Inputs DC Input Current per Pin Power Dissipation per Package (Note 1) Operating Temperature Range Storage Temperature Range Symbol VDD Vin Iin PD TA Tstg Value −0.5 to +18.0 −0.5 to VDD + 0.5 ±10 500 −55 to +125 −65 to +150 Unit V V mA mW °C °C PIN ASSIGNMENT Q4 Q5 Q6 Q7 Sout D C VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q3 Q2 Q1 Q0 EOC * Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 SC *For MC14549B Pin 10 is MR input. For MC14559B Pin 10 is FF input. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. 1 June, 2006 − Rev. 6 Publication Order Number: MC14549B/D MC14549B, MC14559B TRUTH TABLES MC14549B SC SC(t−1) MR MR(t−1) Clock Action X X X X None X X 1 X Reset 1 0 0 0 Start Conversion 1 X 0 1 Start Conversion 1 1 0 0 Continue Conversion 0 X 0 X Continue Previous Operation X = Don’t Care t−1 = State at Previous Clock SC X 1 X 0 0 X 0 1 0 X MC14559B SC(t−1) EOC Clock X 0 0 0 1 Action None Start Conversion Continue Conversion Continue Conversion Retain Conversion Result Start Conversion 1 X 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) (Clock = 0 V, Other Inputs = VDD or 0 V, Iout = 0 mA) Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 5.0 10 15 Iin Cin IDD 15 − 5.0 10 15 5.0 10 15 – 1.2 – 0.25 – 0.62 – 1.8 1.28 3.2 8.4 0.64 1.6 4.2 − − − − − − − − − − − − − − − ± 0.1 − 5.0 10 20 – 1.0 – 0.2 − 0.5 – 1.5 1.02 2.6 6.8 0.51 1.3 3.4 − − − − − – 1.7 – 0.36 – 0.9 – 3.5 1.76 4.5 17.6 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 − − − − − − − − − − ± 0.1 7.5 5.0 10 20 – 0.7 – 0.14 – 0.35 – 1.1 0.72 1.8 4.8 0.36 0.9 2.4 − − − − − − − − − − − − − − − ± 1.0 − 150 300 600 VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − mAd c − 55_C 25_C 125_C Characteristic Symbol VOL Min − − − 4.95 9.95 14.95 − − − Max Min − − − 4.95 9.95 14.95 − − − Typ (Note 2) 0 0 0 5.0 10 15 2.25 4.50 6.75 Max Min − − − 4.95 9.95 14.95 − − − Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 − − − 1.5 3.0 4.0 0.05 0.05 0.05 − − − 1.5 3.0 4.0 0.05 0.05 0.05 − − − 1.5 3.0 4.0 Vdc “1” Level Vin = 0 or VDD Input Voltage (Note 2) (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL VOH Vdc Vdc Sink Q Outputs Sink Pin 5, 11 only mAd c mAd c mAdc pF mAdc IT IT = (0.8 mA/kHz) f + IDD IT = (1.6 mA/kHz) f + IDD IT = (2.4 mA/kHz) f + IDD mAdc 2. Noise immunity specified for worst−case input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V 3. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10−3 (CL = 50) VDDf where: IT is in mA (per package), CL in pF, VDD in V, and f in kHz is input frequency. 4. The formulas given are for the typical characteristics only at 25_C. http://onsemi.com 2 MC14549B, MC14559B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Symbol tTLH VDD 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 tsu 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 − − − − − − − − 250 100 80 700 270 200 500 200 160 − − − − − − 500 210 155 750 310 220 300 130 100 125 50 40 350 135 100 250 100 80 1000 420 310 1500 620 440 600 260 200 − − − − − − − − − 15 1.0 0.5 0.8 1.5 2.0 ns Min − − − − − − Typ 180 90 65 100 50 40 Max 360 180 130 200 100 80 ns Unit ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 177 ns tPLH, tPHL = (0.5 ns/pF) CL + 130 ns Clock to Sout tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 277 ns tPLH, tPHL = (0.5 ns/pF) CL + 195 ns Clock to EOC tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns SC, D, FF or MR Setup Time tTHL ns Clock Pulse Width tWH(cl) ns Pulse Width — D, SC, FF or MR tWH ns Clock Rise and Fall Time tTLH, tTHL fcl ms − 1.5 3.0 4.0 Clock Pulse Frequency MHz 5. The formulas given are for the typical characteristics only. ORDERING INFORMATION Device MC14549BCP MC14549BCPG MC14549BDWR2 MC14549BDWR2G MC14559BCP MC14559BCPG MC14559BDWR2 MC14559BDWR2G Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) 1000 / Tape & Reel 25 / Rail 1000 / Tape & Reel 25 / Rail Shipping † †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 MC14549B, MC14559B SWITCHING TIME TEST CIRCUIT AND WAVEFORMS VDD Q7 C PROGRAMMABLE PULSE GENERATOR SC FF(MR) D Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout VSS CL 50% CL 1 fcl C SC D CL CL CL CL CL CL CL CL tWH(cl) tsu 50% tsu 50% tPLH 50% tTLH 90% tsu tPHL 10% tTHL tPLH 90% 10% tTLH tWH(D) Q7 Sout NOTE: Pin 10 = VSS 50% TIMING DIAGRAM CLOCK SC D Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH — Don’t care condition INH — Indicates Serial Out is inhibited low. * — Q8 is ninth−bit of serial information available from 8−bit register. NOTE: Pin 10 = VSS http://onsemi.com 4 MC14549B, MC14559B OPERATING CHARACTERISTICS Both the MC14549B and MC14559B can be operated in either the “free run” or “strobed operation” mode for conversion schemes with any number of bits. Reliable cascading and/or recirculating operation can be achieved if the End of Convert (EOC) output is used as the controlling function, since with EOC = 0 (and with SC = 1 for MC14549B but either 1 or 0 for MC14559B) no stable state exists under continual clocked operation. The MC14559B will automatically recirculate after EOC = 1 during externally strobed operation, provided SC = 1. All data and control inputs for these devices are triggered into the circuit on the positive edge of the clock pulse. Operation of the various terminals is as follows: C = Clock — A positive−going transition of the Clock is required for data on any input to