(MC14549B / MC14559B) SUCCESSIVE APPROXIMATION REGISTERS

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Successive Approximation Registers The MC14549B and MC14559B successive approximation registers are 8–bit registers providing all the digital control and storage necessary for successive approximation analog–to–digital conversion systems. These parts differ in only one control input. The Master Reset (MR) on the MC14549B is required in the cascaded mode when more than 8 bits are desired. The Feed Forward (FF) of the MC14559B is used for register shortening where End–of–Conversion (EOC) is required after less than eight cycles. Applications for the MC14549B and MC14559B include analog–to–digital conversion, with serial and parallel outputs. • Totally Synchronous Operation • All Outputs Buffered • Single Supply Operation • Serial Output • Retriggerable • Compatible with a Variety of Digital and Analog Systems such as the MC1408 8–Bit D/A Converter • All Control Inputs Positive–Edge Triggered • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–Power TTL Loads, One Low–Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range • Chip Complexity: 488 FETs or 122 Equivalent Gateswww.DataSheet4U.com MAXIMUM RATINGS* (Voltages referenced to VSS) Rating Symbol VDD Vin Iin PD TA Tstg DC Supply Voltage Value Unit Vdc Vdc mAdc mW _C _C MC14549B MC14559B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 0.5 to + 18 ± 10 500 – 55 to + 125 – 65 to + 150 Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation, per Package† Operating Temperature Range Storage Temperature Range – 0.5 to VDD + 0.5 * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: “P and D/DW” Packages: – 7.0 mW/C From 65_ C To 125_ C Ceramic “L” Packages: – 12 mW/_ C From 100_ C To 125_ C PIN ASSIGNMENT Q4 Q5 Q6 Q7 Sout D C VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q3 Q2 Q1 Q0 EOC * SC * For MC14549B Pin 10 is MR input. For MC14559B Pin 10 is FF input. MC14549B TRUTH TABLES MC14559B SC SC(t–1) MR MR(t–1) Clock Action X X X X None X X 1 X Reset 1 0 0 0 Start Conversion 1 X 0 1 Start Conversion 1 1 0 0 Continue Conversion 0 X 0 X Continue Previous Operation X = Don’t Care t–1 = State at Previous Clock REV 3 1/94 SC SC(t–1) EOC Clock Action X X X None 1 0 0 Start Conversion X 1 0 Continue Conversion 0 0 0 Continue Conversion 0 X 1 Retain Conversion Result 1 X 1 Start Conversion ©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14549B MC14559B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 5.0 10 15 Iin Cin IDD 15 — 5.0 10 15 – 1.2 – 0.25 – 0.62 – 1.8 1.28 3.2 8.4 0.64 1.6 4.2 — — — — — — — — — — — — — — — ± 0.1 — 5.0 10 20 – 1.0 – 0.2 – 0.5 – 1.5 1.02 2.6 6.8 0.51 1.3 3.4 — — — — — – 1.7 – 0.36 – 0.9 – 3.5 1.76 4.5 17.6 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 — — — — — — — — — — ± 0.1 7.5 5.0 10 20 – 0.7 – 0.14 – 0.35 – 1.1 0.72 1.8 4.8 0.36 0.9 2.4 — — — — — — — — — — — — — — — ± 1.0 — 150 300 600 mAdc 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — mAdc Min — — — – 55_ C 25_ C 125_ C Max Min — — — Typ # 0 0 0 Max Min — — — Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 Vdc “1” Level Vin = 0 or VDD Input Voltage # “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance Quiescent Current (Per Package) (Clock = 0 V, Other Inputs = VDD or 0 V, Iout = 0 µA) Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL — — — — — — 2.25 4.50 6.75 — — — VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Q Outputs Sink Pin 5, 11 only mAdc µAdc pF µAdc IT 5.0 10 15 IT = (0.8 µA/kHz) f + IDD IT = (1.6 µA/kHz) f + IDD IT = (2.4 µA/kHz) f + IDD µAdc #Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL = 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_ C. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). v v MC14549B MC14559B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_ C) Characteristic Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Symbol tTLH VDD 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 tsu 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 — — — — — — — — 250 100 80 700 270 200 500 200 160 — — — — — — 500 210 155 750 310 220 300 130 100 125 50 40 350 135 100 250 100 80 1000 420 310 1500 620 440 600 260 200 — — — — — — — — — 15 1.0 0.5 0.8 1.5 2.0 ns Min — — — — — — Typ 180 90 65 100 50 40 Max 360 180 130 200 100 80 ns Unit ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 177 ns tPLH, tPHL = (0.5 ns/pF) CL + 130 ns Clock to Sout tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 277 ns tPLH, tPHL = (0.5 ns/pF) CL + 195 ns Clock to EOC tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns SC, D, FF or MR Setup Time tTHL ns Clock Pulse Width tWH(cl) ns Pulse Width — D, SC, FF or MR tWH ns Clock Rise and Fall Time tTLH, tTHL fcl µs — 1.5 3.0 4.0 Clock Pulse Frequency MHz * The formulas given are for the typical characteristics only. MOTOROLA CMOS LOGIC DATA MC14549B MC14559B 3 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS VDD Q7 C SC FF(MR) D Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout CL VSS C SC D 50% tsu 50% tsu 50% tPLH Q7 Sout NOTE: Pin 10 = VSS 50% tTLH 90% tsu tPHL 10% tTHL 50% tPLH 90% 10% tTLH tWH(D) CL 1 fcl CL CL CL CL CL CL CL CL PROGRAMMABLE PULSE GENERATOR tWH(cl) TIMING DIAGRAM CLOCK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOC Sout MC14549B MC14559B 4 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ SC D INH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INH — Don’t care condition INH — Indicates Serial Out is inhibited low. * — Q8 is ninth–bit of serial information available from 8–bit register. NOTE: Pin 10 = VSS MOTOROLA CMOS LOGIC DATA OPERATING CHARACTERISTICS Both the MC14549B and MC14559B can be operated in either the “free run” or “strobed operation” mode for conversion schemes with any number of bits. Reliable cascading and/or recirculating operation can be achieved if the End of Convert (EOC) output is used as the controlling function, since with EOC = 0 (and with SC = 1 for MC14549B but either 1 or 0 for MC14559B) no stable state exists under continual clocked operation. The MC14559B will automatically recirculate after EOC = 1 during externally strobed operation, provided SC = 1. All data and control inputs for these devices are triggered into the circuit on the positive edge of the clock pulse. Operation of the various terminals is as follows: C = Clock — A positive–going transition of the Clock is required for data on any input to be strobed into the circuit. SC = Start Convert — A conversion sequence is initiated on the positive–going transition of the SC input on succeeding clock cycles. D = Data in — Data on this input (usually from a comparator in A/D applications) is also entered into the circuit on a positive–going transition of the clock. This input is Schmitt triggered and synchronized to allow fast response