(MC14518B / MC14520B) Dual Up Counters

MC14518B, MC14520B Dual Up Counters The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4−stage counters. The counter stages are type D flip−flops, with interchangeable Clock and Enable lines for incrementing on either the positive−going or negative−going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi−stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. Features http://onsemi.com MARKING DIAGRAMS 16 PDIP−16 P SUFFIX CASE 648 MC145xxBCP AWLYYWWG 1 16 SOIC−16 DW SUFFIX CASE 751G • • • • Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Internal and External Speeds Logic Edge−Clocked Design — Incremented on Positive Transition of Clock or Negative Transition on Enable • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range • Pb−Free Packages are Available* MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Operating Temperature Range Storage Temperature Range Lead Temperature (8−Second Soldering) Value −0.5 to +18.0 −0.5 to VDD + 0.5 ±10 500 −55 to +125 −65 to +150 260 www.DataSheet4U.com 145xxB AWLYYWWG 1 16 SOEIAJ−16 F SUFFIX CASE 966 1 xx A WL, L YY, Y WW, W G = 18 or 20 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Indicator MC145xxB ALYWG Unit V V mA mW °C °C °C ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2006 1 January, 2006 − Rev. 5 Publication Order Number: MC14518B/D MC14518B, MC14520B PIN ASSIGNMENT CA EA Q0A Q1A Q2A Q3A RA VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RB Q3B Q2B Q1B Q0B EB CB BLOCK DIAGRAM CLOCK 1 2 ENABLE 7 CLOCK 9 10 ENABLE 15 C R Q0 Q1 Q2 Q3 11 12 13 14 C R Q0 Q1 Q2 Q3 3 4 5 6 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE Clock Enable 1 0 X X 0 1 X X Reset 0 0 0 0 0 0 1 Action Increment Counter Increment Counter No Change No Change No Change No Change Q0 thru Q3 = 0 X = Don’t Care http://onsemi.com 2 MC14518B, MC14520B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 — 5.0 10 15 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 0.64 1.6 4.2 — — — — — — — — — — — — ± 0.1 — 5.0 10 20 – 2.4 – 0.51 – 1.3 – 3.4 0.51 1.3 3.4 — — — — — – 4.2 – 0.88 – 2.25 – 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 — — — — — — — ± 0.1 7.5 5.0 10 20 – 1.7 – 0.36 – 0.9 – 2.4 0.36 0.9 2.4 — — — — — — — — — — — — ± 1.0 — 150 300 600 mAdc 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — mAdc Min — — — − 55_C 25_C 125_C Max Min — — — Typ (3.) 0 0 0 Max Min — — — Max Unit Vdc Output Voltage Vin = VDD or 0 “0” Level 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 0.05 0.05 0.05 — — — 1.5 3.0 4.0 Vdc “1” Level Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL — — — — — — 2.25 4.50 6.75 — — — VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD μAdc pF μAdc IT IT = (0.6 μA/kHz) f + IDD IT = (1.2 μA/kHz) f + IDD IT = (1.7 μA/kHz) f + IDD μAdc 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in μA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 3 MC14518B, MC14520B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C) Characteristic All Types Typ (7.) 100 50 40 Symbol tTLH, tTHL VDD 5.0 10 15 Min — — — Max 200 100 80 ns 5.0 10 15 tPHL 5.0 10 15 tw(H) tw(L) fcl 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 — — — 200 100 70 — — — — — — 440 200 140 280 120 90 –5 15 20 330 130 90 100 50 35 2.5 6.0 8.0 — — — 220 100 70 125 55 40 – 45 – 15 –5 650 230 170 — — — 1.5 3.0 4.0 15 5 4 — — — — — — — — — ns — — — 280 115 80 560 230 160 ns Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q/Enable to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Reset to Q tPHL = (1.7 ns/pF) CL + 265 ns tPHL = (0.66 ns/pF) CL + 117 ns tPHL = (0.66 ns/pF) CL + 95 ns Clock Pulse Width tPLH, tPHL Clock Pulse Frequency MHz Clock or Enable Rise and Fall Time tTHL, tTLH μs Enable Pulse Width tWH(E) ns Reset Pulse Width tWH(R) ns Reset Removal Time trem ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 500 μF PULSE GENERATOR ID C Q0 Q1 Q2 E Q3 R VSS 20 ns 50% 90% 10% 20 ns VSS 0.01 μF CERAMIC CL CL CL CL VARIABLE WIDTH Figure 1. Power Dissipation Test Circuit and Waveform http://onsemi.com 4 MC14518B, MC14520B VDD PULSE GENERATOR Q0 Q1 Q2 Q3 VSS CL CL CL Q 20 ns CLOCK INPUT tWH tPLH 20 ns 90% 50% 10% tPHL tWL 90% tr tf VDD VSS C E R CL 50% 10% Figure 2. Switching Time Test Circuit and Waveforms 1 CLOCK ENABLE RESET 1 Q0 MC14518B Q1 Q2 Q3 Q0 Q1 Q2 Q3 23 45 6 78 9 10 11 12 13 14 15 16 17 18 23 45 6 78 901 23 45 6 78 90 1 23 45 6 78 9 10 11 12 13 14 15 0 12 3 4 MC14520B Figure 3. Timing Diagram http://onsemi.com 5 MC14518B, MC14520B Q0 Q1 Q2 Q3 D C RESET R Q Q D C R Q Q D C R Q Q D C R Q Q ENABLE CLOCK Figure 4. Decade Counter (MC14518B) Logic Diagram (1/2 of Device Shown) Q0 Q1 Q2 Q3 D C RESET R Q Q D C R Q Q D C R Q Q D C R Q Q ENABLE CLOCK Figure 5. Binary Counter (MC14520B) Logic Diagram (1/2 of Device Shown) http://onsemi.com 6 MC14518B, MC14520B ORDERING INFORMATION Device MC14518BCP MC14518BCPG MC14518BDW MC14518BDWG MC14518BDWR2 MC14518BDWR2G MC14518BFEL MC14518BFELG MC14520BCP MC14520BCPG MC14520BDW MC14520BDWG MC14520BDWR2 MC14520BDWR2G MC14520BFEL MC14520BFELG Package PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOEIAJ−16 SOEIAJ−16 (Pb−Free) PDIP−16 PDIP−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOIC−16 SOIC−16 (Pb−Free) SOEIAJ−16 SOEIAJ−16 (Pb−Free) Shipping† 500 Units / Rail 500 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 2000 Units / Tape & Reel 2000 Units / Tape & Reel 500 Units / Rail 500 Units / Rail 47 Units / Rail 47 Units / Rail 1000 Units / Tape & Reel 1000 Units / Tape & Reel 2000 Units / Tape & Reel 2000 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 MC14518B, MC14520B PACKAGE DIMENSIONS PDIP−16 P SUFFIX PLASTIC DIP PACKAGE CASE 648−08 ISSUE T −A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALL