2.4 GHz ISM Band Low Power Transceiver

Freescale Semiconductor Technical Data Document Number: MC13191 Rev. 1.3, 08/2005 MC13191 (Scale 1:1) MC13191 2.4 GHz ISM Band Low Power Transceiver Device MC13191 Package Information Plastic Package Case 1311-03 (QFN-32) Ordering Information Device Marking 13191 Package QFN-32 1 Introduction The MC13191 is a short range, low power, 2.4 GHz www.DataSheet4U.com Industrial, Scientific, and Medical (ISM) band transceivers. The MC13191 contains a complete packet data modem which is compliant with the IEEE® 802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 compliance, the MC13192 and Freescale's 802.15.4 MAC software are required. When combined with an appropriate microcontroller (MCU), the MC13191 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point to star networks. Contents 1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 3 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . 11 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15 Applications Information . . . . . . . . . . . . . . . 18 Packaging Information . . . . . . . . . . . . . . . . . 23 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2004, 2005. All rights reserved. Features For more detailed information about MC13191 operation, refer to the MC13191 Reference Manual, part number MC13191RM. Applications include, but are not limited to, the following: • Remote control and wire replacement in industrial systems such as wireless sensor networks • Factory automation and motor control • Energy Management (lighting, HVAC, etc.) • Asset tracking and monitoring Potential consumer applications include: • Home automation and control (lighting, thermostats, etc.) • Human interface devices (keyboard, mice, etc.) • Remote entertainment control • Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2 Features • IEEE 802.15.4 PHY Compliant — 16 Channels — Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode/decode — RX sensitivity of -91 dBm (typical) at 1.0% packet error rate Recommended power supply range: 2.0 to 3.4 V 0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power Buffered transmit and receive data packets for simplified use with low cost MCUs Three power down modes for power conservation: — < 1.0 µA Off current — 2.3 µA Typical Hibernate current — 35 µA Typical Doze current (no CLKO) Two internal timer comparators available to reduce MCU resource requirements Programmable frequency clock output for use by MCU Onboard trim capability for 16 MHz crystal reference oscillator eliminates the need for external variable capacitors and allows for automated production frequency calibration. Seven general purpose input/output (GPIO) signals Operating temperature range: -40 °C to 85 °C Small form factor QFN-32 Package MC13191 Technical Data, Rev. 1.3 2 Freescale Semiconductor • • • • • • • • • • Block Diagrams — — — — RoHS compliant Meets moisture sensitivity level (MSL) 3 260 °C peak reflow temperature Meets lead-free requirements 3 Block Diagrams Figure 2 shows a simplified block diagram of the MC13191 transceiver that meets the requirements of the IEEE 802.15.4 PHY. Figure 3 shows the basic system block diagram for the MC13191 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements. 4 Data Transfer Mode The MC13191 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits wide. 4.1 Packet Structure Figure 4 shows the packet structure of the MC13191 which is consistent with the IEEE 802.15.4 Standard. Payloads of up to 125 bytes are supported. The MC13191 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data. 4.2 Receive Path Description In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. An Energy Detect can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM. The MC13191 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet RAM. The MCU is notified that an entire packet has been received via an interrupt. MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 3 Data Transfer Mode Figure 1 shows energy detection reported power versus input power. Note that the IEEE 802.15.4 Standard accuracy and range limits are shown for reference. -25 Reported Power Level (dBm) -35 -45 -55 -65 -75 -85 -85 802.15.4 Accuracy and Range Requirements -75 -65 -55 -45 -35 -25 -15 Input Pow er Level (dBm) Figure 1. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator MC13191 Technical Data, Rev. 1.3 4 Freescale Semiconductor Data Transfer Mode 4.3 Transmit Path Description For the transmit path, the TX data that was previously stored in TX PAcket RAM is retrieved, formed into packets, spread, and then up-converted to the transmit frequency. Because the MC13191 is used in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13191 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted. Synch & Det Correlator LN A R F IN + R F IN - 1s t IF M ix er IF = 65 M Hz 2nd IF M ix er IF = 1 M Hz P M A Dec im ation F ilter B as eband M ix er M atc hed F ilter P ac k et P roc es s or A nalog R egulator P ow er-U p C ontrol Logic Digital R egulator L Digital R egulator H C ry s tal R egulator R ec eiv e P ac k et R A M R ec eiv e R A M A rbiter VC O R egulator V DDA VBAT T V DDIN T CCA DC D Symbol V DDD V DDV C O AGC P rogram m able P res c aler S equenc e M anager (C ontrol Logic ) R XT XEN V D D LO 2 256 M Hz ÷4 24 B it E v ent T im er SERIAL PERIPHERAL INTERFACE (SPI) 2 P rogram m able T im er C om parators CE M OSI M IS O S P IC LK AT T N R ST X T A L1 X T A L2 C ry s tal O s c illator 16 M Hz S y nth esize r T rans m it P ac k et R A M 1 V DDLO 1 2.45 G Hz V CO T rans m it R A M A rbiter S y m bol G eneration IR Q A rbiter G P IO 1 G P IO 2 G P IO 3 G P IO 4 G P IO 5 G P IO 6 G P IO 7 IR Q PAO+ PAO- PA P has e S hift M odulator MUX C LK O FCS G eneration Header G eneration Figure 2. MC13191 Simplified Block Diagram MC13191 Technical Data, Rev. 1.3 Freescale Semiconductor 5 Data Transfer Mode MC13191 Analog Receiver Digital Transceiver Control Logic SPI and GPIO Microcontroller SPI Timer A/D ROM (Flash) RAM RAM Arbiter IRQ Arbiter Timer CPU Application Network Frequency Generation Analog Transmitter Voltage Regulators Power Up Management Buffer RAM MAC PHY Driver Figure 3. System Level Block Diagram 4 bytes Preamble 1 byte SFD 1 byte FLI 125 bytes maximum Payload Data 2 bytes FCS Figure 4. MC13191 Packet Structure MC13191 Technical Data, Rev. 1.3 6 Freescale Semiconductor Electrical Characteristics 5 Electrical Characteristics 5.1 Maximum Ratings Table 1. Absolute Maximum Ratings Rating Power Supply Voltage RF Input Power Junction Temperature Storage Temperature Range Symbol VBATT, VDDINT Pmax TJ Tstg Value 3.6 10 125 -55 to 125 Unit Vdc dBm °C °C Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN± = 100 V MM, PAO± = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection. 5.2 R