(MBM29SL800TE/BE) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20911-1E FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT MBM29SL800TE/BE-90/10 s DESCRIPTION The MBM29SL800TE/BE are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29SL800TE/BE are offered in a 48-ball FBGA and 45-ball SCSP packages. These devices are designed to be programmed in-system with the standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. VCC Max Address Access Time Max CE Access Time Max OE Access Time 90 ns 90 ns 30 ns MBM29SL800TE/BE-90 MBM29SL800TE/BE-10 100 ns 100 ns 35 ns 1.65 V to 1.95 V s PACKAGES 48-ball Plastic FBGA 45-ball Plastic SCSP (BGA-48P-M20) (WLP-45P-M02) MBM29SL800TE/BE-90/10 (Continued) The standard MBM29SL800TE/BE offer access times 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The device supports pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. Each sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29SL800TE/BE are erased when shipped from the factory. The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally returns to the read mode. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29SL800TE/BE memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29SL800TE/BE-90/10 s FEATURES • 0.23 µm Process Technology • Single 1.8 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard world-wide pinouts 48-ball FBGA (Package suffix : PBT) 45-ball SCSP (Package suffix : PW) • Minimum 100,000 program/erase cycles • High performance 90 ns maximum access time • Sector erase architecture One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection set function by Extended sector Protect command • Fast programming Function by Extended Command • Temporary sector unprotection Temporary sector unprotection via the RESET pin Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29SL800TE/BE-90/10 s PIN ASSIGNMENTS FBGA (TOP VIEW) Marking side A6 A13 A5 A9 A4 B6 A12 B5 A8 B4 C6 A14 C5 A10 C4 D6 A15 D5 A11 D4 N.C. D3 N.C. D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 G6 H6 BYTE DQ15/A-1 VSS F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS WE RESET N.C. A3 RY/BY A2 A7 A1 A3 B3 N.C. B2 A17 B1 A4 C3 A18 C2 A6 C1 A2 (BGA-48P-M20) SCSP (TOP VIEW) Marking side A5 CE A4 VSS A3 A0 A2 A1 A1 A2 B5 OE B4 DQ0 B3 DQ8 B2 A3 B1 A4 C5 DQ1 C4 DQ9 C3 DQ2 C2 A5 C1 A6 D5 DQ10 D4 DQ3 D3 DQ11 D2 A7 D1 A17 E5 VCC E4 DQ4 E3 N.C. E2 A18 E1 RY/BY F5 DQ12 F4 DQ5 F3 A8 F2 RESET F1 WE G5 H5 J5 DQ6 DQ15/A-1 BYTE G4 DQ13 G3 A11 G2 A10 G1 A9 H4 DQ7 H3 DQ14 H2 A13 H1 A12 J4 VSS J3 A16 J2 A15 J1 A14 (WLP-45P-M02) 4 MBM29SL800TE/BE-90/10 s PIN DESCRIPTION Pin name A18 to A0, A-1 DQ15 to DQ0 CE OE WE RESET RY/BY BYTE VCC VSS N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy Output Selects 8-bit or 16-bit mode Device Power Supply Device Ground No Internal Connection Function 5 MBM29SL800TE/BE-90/10 s BLOCK DIAGRAM DQ15 to DQ0 VCC VSS RY/BY Buffer RY/BY Erase Voltage Generator Input/Output Buffers WE BYTE RESET State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Address Latch Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase X-Decoder Cell Matrix A18 to A0 A-1 s LOGIC SYMBOL A-1 19 A18 to A0 DQ15 to DQ0 CE OE WE RESET BYTE RY/BY 16 or 8 6 MBM29SL800TE/BE-90/10 s DEVICE BUS OPERATION MBM29SL800TE/BE User Bus Operations (BYTE = VIH) Operation Standby Autoselect Manufacturer Code * Autoselect Device Code * Read * Write Enable Sector Protection * * Verify Sector Protection * * Reset (Hardware) /Standby 2, 4 5 2, 4 3 1 1 CE H L L L L L L L X X OE X L L L H H H L X X WE X H H H H L L H X X A0 X L H A0 X A0 L L X X A1 X L L A1 X A1 H H X X A6 X L L A6 X A6 L L X X A9 X VID VID A9 X A9 X VID X X DQ15 to DQ0 High-Z Code Code DOUT High-Z DIN X Code X High-Z RESET H H H H H H VID H VID L Output Disable Temporary Sector Unprotection * Legend : L = VIL, H = VIH, X = VIL or VIH, See s DC CHARACTERISTICS. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29SL800TE/BE Standard Command Definitions”. *2: Refer to the section on Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 1.8 V ± 0.15V *5: It is also used for the extended sector protection. MBM29SL800TE/BE User Bus Operations (BYTE = VIL) Operation Standby Autoselect Manufacturer Code * Autoselect Device Code * Read * Write Enable Sector Protection * * Verify Sector Protection * * Reset (Hardware) /Standby 2, 4 5 2, 4 3 1 1 CE H L L L L L L L X X OE X L L L H H H L X X WE X H H H H L L H X X DQ15/ A-1 X L L A-1 X A-1 L L X X A0 X L H A0 X A0 L L X X A1 X L L A1 X A1 H H X X A6 X L L A6 X A6 L L X X A9 X VID VID A9 X A9 VID VID X X DQ7 to DQ0 High-Z Code Code DOUT High-Z DIN X Code X High-Z RESET H H H H H H VID H VID L Output Disable Temporary Sector Unprotection * Legend : L = VIL, H = VIH, X = VIL or VIH, See s DC CHARACTERISTICS. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29SL800TE/BE Standard Command Definitions”. *2: Refer to the section on Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 1.8 V ± 0.15 V *5: It is also used for the extended sector protection. 7 MBM29SL800TE/BE-90/10 MBM29SL800TE/BE Standard Command Definitions *1 Command Sequence Word Bus Write Cycles Req’d First Bus Second Bus Third Bus Write Cycle Write Cycle Write Cycle Fourth Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h AAh AAh AAh AAh AAh  2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h  55h 55h 55h 55h 55h  555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh  F0h 90h A0h 80h 80h  RA 00h PA 555h AAAh 555h AAAh  RD 04h PD AAh AAh     2AAh 555h 2AAh 555h     55h 55h     555h AAAh SA     10h 30h Reset *2 Reset *2 Autoselect Program Chip Erase Sector Erase Byte Word 1 3 3 4 6 6 Byte Word Byte Word Byte Word Byte Word Byte Sector Erase Suspend *3 Erase can be suspended during sector erase with ADDr. (“H” or “L”) . Data (B0h) Sector Erase Resume *3 Erase can be resumed after sector erase suspend with ADDr. (“H” or “L”) . Data (30h)