(MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20871-5E FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT MBM29SL800TD/BD-10/12 s DESCRIPTION The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Ordering Part No. VCC = +2.0 V ± 0.2 Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29SL800TD/MBM29SL800BD −10 100 100 35 −12 120 120 50 s PACKAGES 48-pin Plastic TSOP (I) Marking Side 48-pin Plastic TSOP (I) 48-pin Plastic FBGA 48-pin Plastic SCSP Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-48P-M12) (WLP-48P-M03) MBM29SL800TD-10/12/MBM29SL800BD-10/12 (Continued) The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29SL800TD/BD are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the factory. The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29SL800TD-10/12/MBM29SL800BD-10/12 s FEATURES • Single 1.8 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 48-ball FBGA (Package suffix : PBT) 48-ball SCSP (Package suffix : PW) • Minimum 100,000 program/erase cycles • High performance 100 ns maximum access time • Sector erase architecture One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection set function by Extended sector Protect command • Fast programming Function by Extended Command • Temporary sector unprotection Temporary sector unprotection via the RESET pin Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29SL800TD-10/12/MBM29SL800BD-10/12 s PIN ASSIGNMENTS TSOP (I) A15 A14 A13 A12 A11 A10 A9 A8 N.C. N.C. WE RESET N.C. N.C. RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. N.C. A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M20) (Continued) 4 MBM29SL800TD-10/12/MBM29SL800BD-10/12 (Continued) FBGA (TOP VIEW) Marking side A6 A13 A5 A9 A4 B6 A12 B5 A8 B4 C6 A14 C5 A10 C4 D6 A15 D5 A11 D4 N.C. D3 N.C. D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 G6 H6 BYTE DQ15/A-1 VSS F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS WE RESET N.C. A3 RY/BY A2 A7 A1 A3 B3 N.C. B2 A17 B1 A4 C3 A18 C2 A6 C1 A2 (BGA-48P-M12) SCSP (TOP VIEW) Marking side A6 A3 A5 A7 A4 RY/BY A3 WE A2 A9 A1 A13 B6 A4 B5 A17 B4 N.C. B3 RESET B2 A8 B1 A12 C6 A2 C5 A6 C4 A18 C3 N.C. C2 A10 C1 A14 D6 A1 D5 A5 D4 N.C. D3 N.C. D2 A11 D1 A15 E6 A0 E5 DQ0 E4 DQ2 E3 DQ5 E2 DQ7 E1 A16 F6 CE F5 DQ8 F4 DQ10 F3 DQ12 F2 DQ14 F1 G6 OE G5 DQ9 G4 DQ11 G3 VCC G2 DQ13 G1 H6 VSS H5 DQ1 H4 DQ3 H3 DQ4 H2 DQ6 H1 BYTE DQ15/A-1 VSS (WLP-48P-M03) 5 MBM29SL800TD-10/12/MBM29SL800BD-10/12 s PIN DESCRIPTION Pin name A18 to A0, A-1 DQ15 to DQ0 CE OE WE RESET RY/BY BYTE VSS VCC N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Reset Pin/Temporary Sector Unprotection Ready/Busy Output Selects 8-bit or 16-bit mode Device Ground Device Power Supply No Internal Connection Function 6 MBM29SL800TD-10/12/MBM29SL800BD-10/12 s BLOCK DIAGRAM DQ15 to DQ0 VCC VSS RY/BY Buffer RY/BY Erase Voltage Generator Input/Output Buffers WE BYTE RESET State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Address Latch Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase X-Decoder Cell Matrix A18 to A0 A-1 s LOGIC SYMBOL A-1 19 A18 to A0 DQ15 to DQ0 CE OE WE RESET BYTE RY/BY 16 or 8 7 MBM29SL800TD-10/12/MBM29SL800BD-10/12 s DEVICE BUS OPERATION MBM29SL800TD/800BD User Bus Operations Table (BYTE = VIH) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Protection *2, *4 Verify Sector Protection * * Reset (Hardware) /Standby 2, 4 CE L L L H L L L L X X OE L L L X H H VID L X X WE H H H X H L H X X A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ0 to DQ15 Code Code DOUT High-Z High-Z DIN X Code X High-Z RESET H H H H H H H H VID L Temporary Sector Unprotection MBM29SL800TD/800BD User Bus Operations Table (BYTE = VIL) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read * 3 1 CE L L L H L L 2, 4 OE L L L X H H VID L X X WE H H H X H L H X X DQ15/ A-1 L L A-1 X X A-1 L L X X A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ0 to DQ7 Code Code DOUT High-Z High-Z DIN X Code X High-Z RESET H H H H H H H H VID L Standby Output Disable Write (Program/Erase) Enable Sector Protection * * Verify Sector Protection *2, *4 Temporary Sector Unprotection *5 Reset (Hardware) /Standby Legend : L = VIL, H = VIH, X = VIL or VIH, L L X X = Pulse input. See “sDC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29SL800TD/800BD Standard Command Definitions Table”. *2: Refer to the section on Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 2.0 V ± 10% *5: It is also used for the extended sector protection. 8 MBM29SL800TD-10/12/MBM29SL800BD-10/12 MBM29SL800TD/800BD Standard Command Definitions Table Command Sequence Read/ Reset Read/ Reset Autoselect Program Chip Erase Sector Er