(MBM29PL32TM/BM) FLASH MEMORY CMOS 32 M (4M X 8/2M X 16) BIT MirrorFlash

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20907-3E FLASH MEMORY CMOS 32 M (4M × 8/2M × 16) BIT MirrorFlashTM* MBM29PL32TM/BM 90/10 s DESCRIPTION The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words by 16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. VCC Max Address Access Time Max CE Access Time Max Page Read Access Time MBM29PL32TM/BM 90 3.0 V to 3.6 V 90 ns 90 ns 25 ns 10 3.0 V to 3.6 V 100 ns 100 ns 30 ns s PACKAGES 48-pin plastic TSOP (1) 48-ball plastic FBGA (FPT-48P-M19) * : MirrorFlashTM is a trademark of Fujitsu Limited. (BGA-48P-M20) Notes : • Programming in byte mode ( × 8) is prohibited. • Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same address.) MBM29PL32TM/BM90/10 (Continued) The standard MBM29PL32TM/BM offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29PL32TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS standard. Commands are written into the command register. The register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29PL32TM/BM is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally return to the read mode. Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simultaneously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29PL32TM/BM90/10 s FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Industry-standard pinouts 48-pin TSOP (1) (Package suffix: TN - Normal Bend Type) 48-ball FBGA(Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance Page mode Fast 8 bytes / 4 words access capability • Sector erase architecture Eight 8K byte and sixty-three 64K byte sectors Eight 4K word and sixty-three 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM 256 bytes / 128 words of HiddenROM, accessible through a “HiddenROM Entry” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of outermost two 8K bytes / 4K words sectors, regardless of sector protection/unprotection status At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Program Suspend/Resume Suspends the program operation to allow a read in another address • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector protect command • Fast Programming Function by Extended Command • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin This feature allows code changes in previously locked sectors • In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29PL32TM/BM90/10 s PIN ASSIGNMENTS 48-pin Plastic TSOP(1) (Top View) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 (FPT-48P-M19) 48-ball plastic FBGA (Top View) Marking Side A6 A13 A5 A9 A4 B6 A12 B5 A8 B4 C6 A14 C5 A10 C4 D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1 E6 A16 E5 F6 G6 H6 BYTE DQ15/ VSS A-1 F5 G5 H5 DQ7 DQ14 DQ13 DQ6 E4 F4 G4 VCC G3 H4 DQ4 H3 WE RESET N.C. A3 B3 C3 A18 C2 A6 C1 A2 DQ5 DQ12 E3 F3 RY/BY WP/ ACC A2 A7 A1 A3 B2 A17 B1 A4 DQ2 DQ10 DQ11 DQ3 E2 DQ0 E1 A0 F2 DQ8 F1 CE G2 DQ9 G1 OE H2 DQ1 H1 VSS (BGA-48P-M20) 4 MBM29PL32TM/BM90/10 s PIN DESCRIPTIONS MBM29PL32TM/BM Pin Configuration Pin A20 to A0, A-1 DQ15 to DQ0 CE OE WE WP/ACC RESET BYTE RY/BY VCC VSS N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Write Protection/Program Acceleration Hardware Reset Pin/Temporary Sector Group Unprotection Select Byte or Word mode Ready/Busy Output Device Power Supply Device Ground No Internal Connection Function 5 MBM29PL32TM/BM90/10 s BLOCK DIAGRAM DQ15 to DQ0 VCC VSS Erase Voltage Generator Input/Output Buffers WE RESET WP/ACC BYTE State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Y-Decoder Y-Gating Timer for Program/Erase A20 to A2 A1, A0 (A-1) Address Latch X-Decoder Cell Matrix s LOGIC SYMBOL A-1 21 A20 to A0 DQ 15 to DQ 0 CE OE WE WP/ACC RESET 16 or 8 BYTE RY/BY 6 MBM29PL32TM/BM90/10 s DEVICE BUS OPERATION MBM29PL32TM/BM User Bus Operations (Word Mode : BYTE = VIH) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Program/Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X A0 X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 X L L A6 X A6 L X X X A9 X VID VID A9 X A9 X X X X DQ0 to DQ15 Hi-Z Code Code DOUT Hi-Z *3 *3 *3 Hi-Z X RESET H H H H H H VID VID L H WP/ ACC X X X X X *4 H H X L Legend : L = VIL, H = VIH, X = VIL or VIH. See “s ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Hi-Z = High-Z, VID = 11.5 V to 12.5 V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See “Sector Group Protection Verify Autoselect Codes”. *2 : Refer to “Sector Group Protection” in s FUNCTIONAL DESCRIPTION. *3 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm *4 : If WP/ACC = VIL, the outermost two sectors remain protected. If WP/ACC = VIH, the outermost two sectors will be protected or unprotected as determined by the method specified in “Sector Group Protection” in s FUNCTIONAL DESCRIPTION. 7 MBM29PL32TM/BM90/10 MBM29PL32TM/BM User Bus Operations (Byte Mode : BYTE = VIL) Operation Standby Autoselect Manufacture Code*1 Autoselect Device Code*1 Read Output Disable Write (Erase) Enable Sector Group Protection*2 Temporary Sector Group Unprotection Reset (Hardware) Sector Write Protection CE OE WE H L L L L L L X X X X L L L H H H X X X X H H H H L L X X X DQ15/ A0 A-1 X L L A-1 X A-1 L X X X X L H A0 X A0 L X X X A1 X L L A1 X A1 H X X X A2 X L L A2 X A2 L X X X A3 X L L A3 X A3 L X X X A6 A9 X L L A6 X A6 L X X X X VID VID A9 X A9 X X X X DQ0 to WP/ RESET DQ7 ACC Hi-Z Code Code DOUT Hi-Z *3 *3 *3 Hi-Z X H H H H H H VID VID L H X X X X X *4 H H X L Legend : L = VIL, H = VIH, X = VIL or VIH. See “s ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Hi-Z = High-Z, VID = 11.5 V to 12.5 V *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29PL32TM/BM Standard Command Definitions”. *2 : Refer to “Sector Gro