Description
www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20910-2E BURST MODE FLASH MEMORY CMOS 128M (8M × 16) BIT MBM29BS/FS12DH 15 s DESCRIPTION The MBM29BS/FS12DH is a 128 Mbit, 1.8 Volt-only, Burst mode and dual operation Flash memory organized as 8M words of 16 bits each. The device offered in a 80-ball FBGA package. This device is designed to be programmed in-system with the standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Handshaking On/Off Max Latency (even address in case of Handshaking) Time (ns) Synchronous/Burst Max Burst Access Time (ns) Max OE Access Time (ns) Max Address Access Time (ns) Asynchronous Max CE Access Time (ns) Max OE Access Time (ns) MBM29BS12DH Non-Handshaking 71 11 11 50 50 11 MBM29FS12DH Handshaking 56 11 11 50 50 11 s PACKAGE 80-ball plastic FBGA (BGA-80P-M04) MBM29BS/FS12DH15 (Continued) The device provides truly high performance non-volatile memory solution. The device offers fast burst access frequency of 66 MHz with initial access times of 56 ns at Handshaking mode, allowing operation of high-speed microprocessors without wait states. To eliminate bus connection the device has separate chip enable (CE), write enable (WE), address valid (AVD) and output enable (OE) controls. For burst operations, the device additionally requires Ready (RDY) at Handshaking mode, and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/ microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space. At 66 MHz, the device provides a burst access of 11 ns with a latency of 56 ns at 30 pF (Handshaking mode). The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The Enhanced VI/O (VCCQ) feature allows the output voltage generated on the device to be determined based on the VI/O level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 MBM29BS/FS12DH15 s FEATURES • • • • 0.13 µm process technology Single 1.8 V read, program and erase (1.65 V to 1.95 V) Simultaneous Read/Write operation (Dual Bank) FlexBankTM*1 Bank A: 16 Mbit (4 Kwords × 8 and 32 Kwords × 31) Bank B: 48 Mbit (32 Kwords × 96) Bank C: 48 Mbit (32 Kwords × 96) Bank D: 16 Mbit (4 Kwords × 8 and 32 Kwords × 31) Enhanced VI/OTM*2 (VCCQ) Feature Input/ Output voltage generated on the device is determined based on the VI/O level High Performance Burst frequency reach at 66 MHz Burst access times of 11 ns @ 30 pF at industrial temperature range Asynchronous random access times of 50 ns (at 30 pF) Synchronous latency of 56 ns with 1.8 V VCCQ for Handshaking mode Programmable Burst Interface Linear Burst: 8, 16, and 32 words with wrap-around Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Minimum 100,000 program/erase cycles Sector Erase Architecture Eight 4 Kwords, two hundred fifty-four 32 Kwords sectors, eight 4 Kwords sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. HiddenROM region 64 words for factory and 64 words for customer of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a sector secure serial number (ESN) Write Protect Pin (WP) At VIL, allows protection of “outermost” 4×4 K words on low, high end or both ends of boot sectors, regardless of sector protection/unprotection status Accelerate Pin (ACC) At VACC, increases program performance. ; all sectors locked when ACC = VIL Embedded EraseTM*2 Algorithms Automatically preprograms and erases the chip or any sector Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready Output (RDY) In Synchronous Mode, indicates the status of the Burst read. In Asynchronous Mode, indicates the status of the internal program and erase function. Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device In accordance with CFI (Common Flash Interface) Hardware reset pin (RESET) Hardware method to reset the device for reading array data • • • • • • • • • • • • • • • • • *1 : FlexBankTM is a trademark of Fujitsu Limited. *2 : Embedded EraseTM, Embedded ProgramTM and Enhanced VI/OTM are trademarks of Advanced Micro Devices, Inc. (Continued) 3 MBM29BS/FS12DH15 (Continued) • Sector Protection Persistent sector protection Password sector protection ACC protects all sectors WP protects the outermost 4 x 4 K words on both ends of boot sectors, regardless of sector protection / unprotection status. • Handshaking feature available (MBM29FS12DH) Provides host system with minimum possible latency by monitoring RDY • CMOS compatible inputs, CMOS compatible outputs 4 MBM29BS/FS12DH15 s PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A8 N.C. A7 N.C. B8 N.C. B7 N.C. C8 N.C. C7 A13 C6 A9 C5 WE C4 RDY C3 A7 A2 N.C. A1 N.C. B2 N.C. B1 N.C. C2 A3 C1 N.C. D8 A22 D7 A12 D6 A8 D5 RESET D4 ACC D3 A17 D2 A4 D1 VCC E8 N.C. E7 A14 E6 A10 E5 A21 E4 A18 E3 A6 E2 A2 E1 CLK F8 VCCQ F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 WP G8 VSSQ G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 G1 AVD H8 N.C. H7 N.C. H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE H1 VCCQ J8 N.C. J7 DQ15 J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE J1 VSSQ K8 N.C. K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS K1 N.C. L8 N.C. L7 N.C. M8 N.C. M7 N.C. L2 N.C. L1 N.C. M2 N.C. M1 N.C. (BGA-80P-M04) s PIN DESCRIPTIONS Pin name A22 to A0 DQ15 to DQ0 CLK CE OE WE AVD RDY RESET WP ACC N.C. VSS VCC VSSQ VCCQ MBM29BS/FS12DH Pin Configuration Table Function Address Inputs Data Inputs/Outputs CLK Input Chip Enable Output Enable Write Enable Address Valid Input Ready Output. (In asynchronous mode, RY/BY Output) Hardware Reset Hardware Write Protection Program Acceleration Pin Not Connected Internally Device Ground Device Power Supply Input & Output Buffer Ground Input & Output Buffer Power Supply 5 MBM29BS/FS12DH15 s BLOCK DIAGRAM VCC VSS VCCQ VSSQ A22 to A0 Y-Gating Cell Matrix 16 Mbit (Bank A) X-Decoder Cell Matrix 48 Mbit (Bank B) X-Decoder Bank B Address RESET WE CE OE WP AVD CLK ACC State Control & Command Register RDY Status Control Bank C Address DQ15 to DQ0 X-Decoder Y-Gating Cell Matrix 16 Mbit (Bank D) X-Decoder Cell Matrix 48 Mbit (Bank C) Y-Gating Bank D address s LOGIC SYMBOL 23 A22 to A0 DQ15 to DQ0 CLK WP ACC CE OE WE RESET AVD RDY 16 6 Y-Gating Bank A address MBM29BS/FS12DH15 s DEVICE BUS OPERATION MBM29BS/FS12DH User Bus Operations Table Operation CE OE WE WP ACC A22 to A0 DQ15 to DQ0 CLK AVD RESET Asynchronous Mode Operations (Default) Asynchronous Read Addresses Latched *1 Standby Output Disable Write - WE address latched * 3 3 L H L L L X X X L X H H H X X X H X H L X X X X X X X* X* L X X 2 2 X X X H* H* X L X 2 2 Addr In X X Addr In Addr In X X X DOUT High-Z High-Z DIN DIN X X High-Z X X X X X X X X L

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MBM29BS12DH

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