(MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20876-3E FLASH MEMORY CMOS 4 M (512 K × 8) BIT MBM29F004TC/004BC-70/-90 s DESCRIPTION The MBM29F004TC/BC is a 4 M-bit, 5.0 V-Only Flash memory organized as 512 K bytes of 8 bits each. The MBM29F004TC/BC is offered in a 32-pin TSOP (1) and 32-pin QFJ (PLCC) packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F004TC/BC offers access times between 70 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29F004TC/BC is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. (Continued) s PRODUCT LINE UP Part No. Ambient Temperature ( °C) Max Address Access Time (ns) VCC Supply Voltage Operation Erase/Program Voltage Consumption (mW) (Max) TTL Standby mode CMOS Standby mode Max CE Access (ns) Max OE Access (ns) 70 30 MBM29F004TC/BC -70 −20 to + 70 70 5.0 V ± 10% 193 275 5.5 0.0275 90 35 -90 −40 to + 85 90 MBM29F004TC/004BC-70/90 (Continued) The MBM29F004TC/BC is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. Any individual sector is typically erased and verified within 1.0 second (if already completely preprogrammed) . This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29F004TC/BC is erased when shipped from the factory. The MBM29F004TC/BC device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. True background erase can thus be achieved. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ7, or by the Toggle Bit I feature on DQ6 output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29F004TC/BC memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. s PACKAGE 32-pin plastic TSOP (1) Marking Side 32-pin plastic TSOP (1) 32-pin plastic QFJ (PLCC) Marking Side (FPT-32P-M24) (FPT-32P-M25) (LCC-32P-M02) 2 MBM29F004TC/004BC-70/90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection • 32-pin TSOP (1) (Package Suffix : PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix : PD) • Minimum 100,000 write/erase cycles • High performance 70 ns maximum access time • Flexible sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and seven 64 K bytes sectors Any combination of sectors can be erased. Also supports full chip erase. • Embedded Erase™* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded Program™* Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Low VCC write inhibit ≤ 3.2 V • Erase Suspend/Resume Supports reading or programming data to a sector not being erased • Sector Protection Hardware sector protect that disables any combination of sectors from write or erase operations • Temporary Sector Unprotection Temporary sector unprotection via the command sequence • Boot Code Sector Architecture • Fast Programming • Extended Sector Protection *: Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc. 3 MBM29F004TC/004BC-70/90 s PIN ASSIGNMENTS TSOP (1) A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Marking Side) Normal Bend 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 (FPT-32P-M24) A4 A5 A6 A7 A12 A15 A16 A18 VCC WE A17 A14 A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 CE A10 OE (FPT-32P-M25) (Continued) 4 MBM29F004TC/004BC-70/90 (Continued) PLCC (TOP VIEW) VCC WE 31 A12 A15 A16 A18 A17 30 29 28 27 26 25 24 23 22 21 14 DQ1 15 DQ2 16 VSS 17 DQ3 18 DQ4 19 DQ5 20 DQ6 A14 A13 A8 A9 A11 OE A10 CE DQ7 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 3 2 1 32 (LCC-32P-M02) s PIN DESCRIPTION Table 1 Pin A18 to A0 DQ7 to DQ0 CE OE WE VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable/Sector Protection Unlock Device Ground Device Power Supply (5.0 V±10%) MBM29F004TC/BC Pin Configuration Function 5 MBM29F004TC/004BC-70/90 s BLOCK DIAGRAM VCC VSS Erase Voltage Generator DQ7 to DQ0 Input/Output Buffers State Control WE Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase Address X-Decoder Latch 4,194,304 Cell Matrix A18 to A0 s LOGIC SYMBOL 19 A18 to A0 DQ7 to DQ0 CE OE WE 8 6 MBM29F004TC/004BC-70/90 s DEVICE BUS OPERATION Table 2 MBM29F004TC/BC User Bus Operations Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*2 Standby Output Disable Write (Program/Erase) Enable Sector Protection*3 3-Byte Sector Unlock Sequence 2-Byte Sector Relock Sequence Command Mode Sector Protect*2 Verify Sector Protect*2, *5 Hardware Sector Protect* 2 CE L L L H L L L L L L L H L L OE L L L X H H VID VID VID VID L VID L VID WE H H H X H L A0 L H A0 X X A0 X A0 A0 A0 A1 L L A1 X X A1 X A1 A1 A1 A1 X H A1 A6 L L A6 X X A6 X A6 A6 A6 A6 L L A6 A9 VID VID A9 X X A9 VID A9 A9 A9 A9 VID VID A9 I/O Code Code DOUT High-Z High-Z DIN X DIN DIN DIN Code X Code DIN H L H A0 X L A0 Verify Sector Protection* * 2, 6 Temporary Sector Unprotection*3 Legend : L = VIL, H = VIH, X = “H” or “L”, = Pulse Input. See DC Characteristics for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 6. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Refer to the section on Sector Protection. *4 : To activate the command, OE has to be taken to VID. *5 : In case of Command Mode Sector Protect. *6 : In case of Hardware Sector Protect. 7 MBM29F004TC/004BC-70/90 Table 3 Command Sequence *1, *2, *3 Read/Reset *1 Read/Reset Byte *1 Auto-Select Manufacture Code Auto-Select Device Code Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Set to Fast Mode Temporary Sector Unprotection Mode *2 Reset from fast Mode *8 Sector Unlock *9 Fast Programming *3 Sector Relock *2 Sector Protection Set Function by Extended Sector Protection Command *2 Extended sector Protection 3 3 2 3 2 2 MBM29F004TC/BC Command Definitions Second Fourth Bus Bus First Bus Third Bus Fifth Bus Sixth Bus Bus Read/Write Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 3 4 6 6 XXXh F0h 555h 555h 555h 555h 555h 555h   55h 55h 55h 55h 55h 55h  555h 555h 555h  F0h F0h 90h  RA 00h 01h PA  RD 04h ID PD                555h SA      10h 30h AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh 555h A0h 555h 555h 80h 80h 555h AAh 2AAh 55h 555h AAh 2AAh 55h Erase can be suspended during sector erase with Addr (“H” or “L”) , Data (B0h) Erase can be resumed after suspend with Addr (“H” or “L”) , Data (30h) 555h 555h AAh 2AAh AAh 2AAh 55h 55h 555h 555h  555h   20h 20h  24h                                       XXXh 90h XXXh 00h 555h AAh 2AAh PA 55h PD F0h or 00h XXXh A0h XXXh 90h XXXh 3 555