(MBM29DL34BF/TF) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20908-2E FLASH MEMORY CMOS 32 M (4 M × 8/2 M × 16) BIT Dual Operation MBM29DL34TF/BF 70 s DESCRIPTION The MBM29DL34TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Power Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29DL34TF/BF 70 2.7 V to 3.6 V 70 70 30 s PACKAGES 48-pin plastic TSOP (1) Marking side 48-ball plastic FBGA (FPT-48P-M19) (BGA-48P-M12) MBM29DL34TF/BF70 ) (Continued) MBM29DL34TF/BF are organized into two physical banks; Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the device, a design concept called Sliding Bank Architecture is implemented. Using this concept the device can execute simultaneous operation between Bank 1 and Bank 2(Refer to “1. Simultaneous Operation” in “s FUNCTIONAL DESCRIPTION”.). The standard device offers access times 70 ns allowing operation of high-speed microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable (OE) controls. The MBM29DL34TF/BF support pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin. Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) . The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally return to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the Embedded ProgramTM * Algorithm or Embedded EraseTM * Algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. These locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/ word at a time using the EPROM programming mechanism of hot electron injection. *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL34TF/BF70 s FEATURES • 0.17 µm Process Technology • Simultaneous Read/Write Operations (Dual Bank) Bank 1 : 8 Mbit Bank 2 : 24 Mbit Host system can program or erase in one bank, then immediately and simultaneously read and from the other bank. Zero latency between read and write operation. Read - while - erase Read - while - program • Single 3.0 V Read, Program, and Erase Minimizes system level power requirements • Compatible with JEDEC-standard Commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard World-wide Pinouts 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 70 ns maximum access time • Sector Erase Architecture Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device (Continued) 3 MBM29DL34TF/BF70 (Continued) • Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. Bank and Sector Organization Table Device Part Number MBM29DL34TF MBM29DL34BF Bank 1 Bank A (SA70 to 48) Bank A (SA0 to 22) Bank 2 Bank B (SA47 to 0) Bank B (SA23 to 70) 4 MBM29DL34TF/BF70 s PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend (FPT-48P-M19) (Continued) 5 MBM29DL34TF/BF70 (Continued) FBGA (TOP VIEW) Marking side A6 A13 A5 A9 A4 WE A3 B6 A12 B5 A8 B4 RESET B3 C6 A14 C5 A10 C4 N.C. C3 A18 C2 A6 C1 A2 D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0 F6 G6 H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS BYTE DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE RY/BY WP/ACC A2 A7 A1 A3 B2 A17 B1 A4 (BGA-48P-M12) 6 MBM29DL34TF/BF70 s PIN DESCRIPTION Pin A20 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC VCC VSS N.C. Address Input Data Input/Output Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects Byte (8-bit) or Word (16-bit) mode Hardware Write Protection/Program Acceleration Device Power Supply Device Ground No Internal Connection Function s LOGIC SYMBOL A-1 21 A20 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8 7 MBM29DL34TF/BF70 s BLOCK DIAGRAM VCC VSS Bank 2 Address A20 to A0 (A-1) Cell Matrix (Bank 2) X-Decoder RY/BY State Control & Command Register Status Control DQ15 to DQ0 RESET WE CE OE BYTE WP/ACC DQ15 to DQ0 X-Decoder Y-Gating & Data Latch Bank 1 Address Cell Matrix (Bank 1) 8 Y-Gating & Data Latch MBM29DL34TF/BF70 s DEVICE BUS OPERATION MBM29DL34TF/BF User Bus Operations Table (Word Mode : BYTE = VIH) Operation Standby Autoselect Manufacturer Code *1 Autoselect Device Code *1 Extended Auto-Select Device Code *1 Read * 3 CE OE WE H L L L L L L L L L X X X X L L L L L H H VID L X X X X H H H H H H L L H X X X A0 X L H L H A0 X A0 L L X X X A1 X L L H H A1 X A1 H H X X X A2 X L L H H A2 X A2 L L X X X A3 X L L H H A3 X A3 L L X X X A6 X L L L L A6 X A6 L L X X X A9 X VID