(MBM29DL32xTE/BE) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20881-7E FLASH MEMORY CMOS 32 M (4 M × 8/2 M × 16) BIT Dual Operation MBM29DL32XTE/BE80/90 s DESCRIPTION The MBM29DL32XTE/BE are a 32 M-bit, 3.0 V-only Flash memory organized as 4 Mbytes of 8 bits each or 2 Mwords of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (Continued) s PRODUCT LINE UP Part No. Power Supply Voltage VCC (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MBM29DL32XTE/BE 80 3.3 +0.3 −0.3 90 3.0 +0.6 −0.3 80 80 30 90 90 35 s PACKAGES 48-pin plastic TSOP (1) Marking Side 48-pin plastic TSOP (1) 63-ball plastic FBGA Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-63P-M01) MBM29DL32XTE/BE80/90 (Continued) In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size combinations; 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb. To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Typically, each sector can be programmed and verified in about 0.5 seconds. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the factory. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29DL32XTE/BE80/90 s FEATURES • 0.23 µm Process Technology • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to “MBM29DL32XTE/BE Device Bank Divisions” in “s FEATURES”) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 63-ball FBGA (Package suffix : PBT) • Minimum 100,000 program/erase cycles • High performance 80 ns maximum access time • Sector erase architecture Eight 4 Kword and sixty-three 32 Kword sectors in word mode Eight 8 Kbyte and sixty-three 64 Kbyte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM region 64 Kbyte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status At VACC, increases program performance • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector group protection Hardware method disables any combination of sector groups from program or erase operations Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. (Continued) 3 MBM29DL32XTE/BE80/90 (Continued) • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) MBM29DL32XTE/BE Device Bank Divisions Device Part Number MBM29DL322TE/BE MBM29DL323TE/BE × 8/× 16 Organization Bank 1 Megabits 4 Mbit 8 Mbit Sector sizes Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, thirty-one 64 Kbyte/ 32 Kword Megabits 28 Mbit 24 Mbit Bank 2 Sector sizes Fifty-six 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Thirty-two 64 Kbyte/32 Kword MBM29DL324TE/BE 16 Mbit 16 Mbit 4 MBM29DL32XTE/BE80/90 s PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M20) (Continued) 5 MBM29DL32XTE/BE80/90 (Continued) FBGA (TOP VIEW) (Marking Side) A8 N.C.* A7 N.C.* B8 N.C.* B7 N.C.* C7 A13 C6 A9 C5 WE C4 D7 A12 D6 A8 D5 RESET D4 E7 A14 E6 A10 E5 N.C. E4 A18 E3 A6 E2 A2 F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 H7 J7 K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS L8 N.C.* L7 N.C.* M8 N.C.* M7 N.C.* BYTE DQ15/A-1 H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE RY/BY WP/ACC C3 A7 A2 N.C.* A1 N.C.* B1 N.C.* C2 A3 D3 A17 D2 A4 L2 N.C.* L1 N.C.* M2 N.C.* M1 N.C.* (BGA-63P-M01) * : Peripheral Balls on each corner are shorted together via substrate but not connected to the die. 6 MBM29DL32XTE/BE80/90 s PIN DESCRIPTIONS MBM29DL32XTE/BE Pin Configuration Pin Name A20 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC N.C. VSS VCC Address Input Data Input/Output Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration No Internal Connection Device Ground Device Power Supply Function 7 MBM29DL32XTE/BE80/90 s BLOCK DIAGRAM VCC VSS Bank 2 Address A20 to A0 (A-1) Cell Matrix (Bank 2) X-Decoder RY/BY State Control & Command Register Status Control DQ15 to DQ0 RESET WE CE OE BYTE WP/ACC DQ15 to DQ0 X-Decoder Y-Gating & Data Latch Bank 1 Address Cell Matrix (Bank 1) s LOGIC SYMBOL A-1 21 A20 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8 8 Y-Gating & Data Latch MBM29DL32XTE/BE80/90 s DEVICE BUS OPERATION MBM29DL32XTE/BE User Bus Operations (BYTE = VIH) Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection*2, *4 Verify Sector Group Protection* * Reset (Hardware) /Standby Boot Block Sector Write Protection Legend : L = VIL, H = VIH, X = VIL or VIH, 2, 4 5 CE OE WE L L L H L L L L X X X L L L X H H VID L X X X H X X X H H H X H L A0 L H A0 X X A0 L L X X X A1 L L A1 X X A1 H H X X X A6 L L A6 X X A6 L L X X X A9 VID VID A9 X X A9 VID VID X X X DQ15 to RESET WP/ACC DQ0 Code Code DOUT High-Z High-Z DIN X Code X High-Z X H H H H H H H H VID L X X X X X X X X X X X L Temporary Sector Group Unprotection* = Pulse input. See DC Characteristics for voltage levels. *1 : Manufacturer and device codes are accessed via a command register write sequence. See “MBM29DL32XTE/ BE Command Definitions”. *2 : Refer to the section on Sector Group Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 3.3 V ± 10% *5 : Also used for the extended sector group protection. 9 MBM29DL32XTE/BE80/90 MBM29DL32XTE/BE User Bus Operations (BYTE = VIL) Operation Auto-Select Manufacturer Code*1