Description
www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20874-7E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29DL16XTD/BD -70/90 s FEATURES Dual Operation • 0.33 µm Process Technology • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to “MBM29DL16XTD/BD Device Bank Divisions Table” in sGENERAL DESCRIPTION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Single 3.0 V read, program, and erase Minimizes system level power requirements (Continued) s PRODUCT LINE UP Part No. Ordering Part No. VCC = 3.3 V VCC = 3.0 V +0.3 V –0.3 V +0.6 V –0.3 V MBM29DL16XTD/MBM29DL16XBD 70 — 70 70 30 — 90 90 90 35 Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) s PACKAGES 48-pin plastic TSOP (1) Marking Side 48-pin plastic TSOP (1) 48-ball plastic FBGA Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-48P-M13) MBM29DL16XTD/BD-70/90 (Continued) • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 70 ns maximum access time • Sector erase architecture Eight 4K word and thirty one 32K word sectors in word mode Eight 8K byte and thirty one 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM region 64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector group protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL16XTD/BD-70/90 s GENERAL DESCRIPTION The MBM29DL16XTD/BD are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTD/BD are offered in a 48-pin TSOP(1) and 48-ball FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL16XTD/BD are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the MBM29DL16XTD/BD, a new design concept is implemented, so called “Sliding Bank Architecture”. Under this concept, the MBM29DL16XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb. The standard MBM29DL16XTD/BD offer access times 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29DL16XTD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29DL16XTD/BD are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL16XTD/BD are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL16XTD/BD memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 3 MBM29DL16XTD/BD-70/90 MBM29DL16XTD/BD Device Bank Divisions Table Device Part Number MBM29DL161TD/BD MBM29DL162TD/BD × 8/× 16 MBM29DL163TD/BD MBM29DL164TD/BD 4 Mbit 8 Mbit Organization Bank 1 Megabits 0.5 Mbit 2 Mbit Sector Sizes Eight 8K byte/4K word Eight 8K byte/4K word, three 64K byte/32K word Eight 8K byte/4K word, seven 64K byte/32K word Eight 8K byte/4K word, fifteen 64K byte/32K word Megabits 15.5 Mbit 14 Mbit 12 Mbit 8 Mbit Bank 2 Sector Sizes Thirty-one 64K byte/32K word Twenty-eight 64K byte/32K word Twenty-four 64K byte/32K word Sixteen 64K byte/32K word 4 MBM29DL16XTD/BD-70/90 s PIN ASSIGNMENTS TSOP(1) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ 15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend FPT-48P-M19 A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 Reverse Bend FPT-48P-M20 (Continued) 5 MBM29DL16XTD/BD-70/90 (Continued) FBGA (TOP VIEW) Marking side A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 (BGA-48P-M13) A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY A18 N.C. DQ2 DQ10 DQ11 DQ3 A4 C4 D4 E4 F4 G4 H4 WE RESET N.C. A19 DQ5 DQ12 VCC DQ4 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 BYTE DQ15/A-1 VSS WP/ACC B4 s PIN DESCRIPTIONS Pin A19 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC N.C. VSS VCC 6 Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration No Internal Connection Device Ground Device Power Supply Function MBM29DL16XTD/BD-70/90 s BLOCK DIAGRAM V CC V SS Bank 2 Address A19 to A0 (A-1) Cell Matrix (Bank 2) X-Decoder RY/BY State Control & Command Register Status Control DQ 15 to DQ 0 RESET WE CE OE BYTE WP/ACC DQ 15 to DQ0 X-Decoder Y-Gating & Data Latch Bank 1 Address Cell Matrix (Bank 1) s LOGIC SYMBOL A-1 20 A19 to A0 DQ 15 to DQ 0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8 Y-Gating & Data Latch 7 MBM29DL16XTD/BD-70/90 s DEVICE BUS OPERATION MBM29DL16XTD/BD User Bus Operations Table (BYTE = VIH) Operation Auto-Select Manufacturer Code*1 Auto-Select Device

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MBM29DL164BD

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