BURST MODE FLASH MEMORY CMOS 32M (2M X 16) BIT

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20913-2E BURST MODE FLASH MEMORY CMOS 32M (2M × 16) BIT MBM29BS/BT32LF 18/25 s GENERAL DESCRIPTION The MBM29BS/BT32LF is a 32M bit, 1.8 Volt-only, Burst mode and dual operation Flash memory organized as 2M words of 16 bits each. The device offered in a 60-ball FBGA package. This device is designed to be programmed in-system with the standard system 1.8V VCC supply. (Continued) s PRODUCT LINE UP Part No. VCC VCCQ Clock Rate Max Latency Time (ns) Synchronous/Burst Max Burst Access Time (ns) Max OE Access Time (ns) Max Address Access Time (ns) Asynchronous Max CE Access Time (ns) Max OE Access Time (ns) MBM29BS/ BT32LF-25 1.8 V +0.15 V –0.15 V MBM29BT32LF-18 MBM29BS32LF-18 1.8 V 3.0 V +0.15 V –0.15 V +0.15 V –0.30 V 1.8 V 1.8 V +0.15 V –0.15 V +0.15 V –0.15 V 1.8 V/3.0 V 40 MHz ( − 25) 120 20 20 70 70 20.5 54 MHz ( − 18) 106.5 14 14 70 70 20 54 MHz ( − 18) 106 13.5 13.5 70 70 20 s PACKAGE 60-ball plastic FBGA (BGA-60P-M05) MBM29BS/BT32LF-18/25 (Continued) The device supports Enhanced VCCQ to offer up to 3 V compatible inputs and outputs(MBM29BS32LF:1.8V VCCQ, MBM29BT32LF:3.0V VCCQ). 12.0V VPP and 5.0V VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device provides truly high performance non-volatile memory solution. The device offers fast burst access frequency of 54MHz with initial access times of 106ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus connection the device has separate chip enable (CE), write enable (WE), address valid (AVD) and output enable (OE) controls. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/ microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space. At 54 MHz, the device provides a burst access of 13.5 ns with a latency of 106 ns at 30 pF. The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0V and 12.0V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.2 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The Enhanced VI/O (VCCQ) feature allows the output voltage generated on the device to be determined based on the VI/O level. This feature allows this device to operate in the 1.8 V and 3.0 V I/O environment, driving and receiving signals to and from other 1.8 V and 3.0 V devices on the same bus. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 MBM29BS/BT32LF-18/25 s FEATURES • • • • 0.17 µm process technology Single 1.8 volt read, program and erase (1.65 V to 1.95 V) Simultaneous Read/Write operation (Dual Bank) All Sectors Being Protected Upon Power-up The device aims for high-speed read of stored codes, thus to fully prevent it from much anticipated wrong operational procedures, programming and erasure, it adopts All-Sectors Lock for ultimate all sector protection by default upon power-up. FlexBankTM *1 Bank A: 8M bit (8K words × 4 and 32K words × 15) Bank B: 8M bit (32K words × 16) Bank C: 8M bit (32K words × 16) Bank D: 8M bit (8K words × 4 and 32K words × 15) Enhanced I/OTM *2 (VCCQ) Feature Input/ Output voltage generated on the device is determined based on the VI/O level (MBM29BS32LF: 1.8V VCCQ and MBM29BT32LF: 3.0V VCCQ) High Performance Burst frequency reach at 54MHz Burst access times of 13.5 ns @ 30 pF at industrial temperature range Asynchronous random access times of 70 ns (at 30 pF) Synchronous latency of 106 ns with 1.8 V VCCQ, and 106.5 ns with 3.0 V VCCQ (at 30 pF) Programmable Burst Read Interface Linear Burst: 8, 16, and 32 words with wrap-around Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Minimum 100,000 program/erase cycles Sector Erase Architecture Eight 8K words, sixty-two 32K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. Write Protect Pin (WP) At VIL, allows protection of “outermost” 2 × 8K words on low end of boot sectors(SA0 and SA1), regardless of sector protection/unprotection status Accelerate Pin (ACC) At VACC, increases program performance. At VIL, hardware protect method to lock all sectors. Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device In accordance with CFI (Common Flash Interface) Hardware reset pin (RESET) Hardware method to reset the device for reading array data To avoid initiation of a write cycle during Vcc power-up/down, Reset must be VIL for defined time. (Continued) • • • • • • • • • • • • • • • • 3 MBM29BS/BT32LF-18/25 (Continued) • Protection Software command sector locking WP protects the outermost two boot sectors(SA0 and SA1) ACC protects all sector at VIL. Should be at VIH for all other conditions. • CMOS compatible inputs, CMOS compatible outputs *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM, Embedded ProgramTM and Enhanced VI/OTM are trademarks of Advanced Micro Devices, Inc. s PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side B8 N.C. A7 A13 A6 A9 A5 WE A4 RDY A3 A7 A2 A3 B7 A12 B6 A8 B5 RESET B4 ACC B3 A17 B2 A4 B1 C8 N.C. C7 A14 C6 A10 C5 N.C. C4 A18 C3 A6 C2 A2 C1 CLK D8 VCCQ D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 WP E8 VSSQ E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 AVD F8 N.C. F7 N.C. F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE F1 VCCQ G8 N.C. G7 DQ15 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE G1 VSSQ H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS Index VCC (BGA-60P-M05) 4 MBM29BS/BT32LF-18/25 s PIN DESCRIPTIONS Pin A20 to A0 DQ15 to DQ0 CLK CE OE WE AVD RDY RESET WP ACC N.C. VSS VCC VSSQ VCCQ Address Inputs Data Inputs/Outputs CLK Input Chip Enable Output Enable Write Enable Address Valid Input Ready Output Hardware Reset Hardware Write Protection Program Acceleration Pin Not Connected Internally Device Ground Device Power Supply Input & Output Buffer Ground Input & Output Buffer Power Supply Function 5 MBM29BS/BT32LF-18/25 s BLOCK DIAGRAM VCC VSS VCCQ VSSQ A20 to A0 Y-Gating Cell Matrix 16 Mbit (Bank A) X-Decoder Cell Matrix 16 Mbit (Bank B) X-Decoder Bank B Address RESET WE CE OE WP AVD CLK ACC State Control & Command Register RDY Status Control Bank C Address DQ15 to DQ0 X-Decoder X-Decoder Y-Gating Bank D address Cell Matrix 16 Mbit (Bank D) Cell Matrix 16 Mbit (Bank C) s LOGIC SYMBOL 21 A20 to A0 DQ15 to DQ0 CLK WP ACC CE OE WE RESET AVD RDY 16 6 Y-Gating Y-Gating Bank A address MBM29BS/BT32LF-18/25 s DEVICE BUS OPERATIONS MBM29BS/BT32LF User Bus Operations Table Operation Auto-Select Manufacturer Code *2 Auto-Select Device Code *2 Extended Auto-Select Device Code *2 Asynchronous Read Addresses Latched *3 Asynchronous Read Addresses Steady State *3 Load Starting Burst Address (CLK latch) *3 Load Starting Burst Address (AVD latch) *3 Advance Burst to next address *3 Terminate Burst read Terminate Burst read an