On-screen Display Controller

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-28826-5E ASSP For Screen Display Control CMOS On-screen Display Controller MB90096 s DESCRIPTION The MB90096 is a multi-scan on-screen display controller that supports horizontal sync signal frequencies of 15 kHz to 120 kHz.The on-screen display configuration is up to 32 characters x 16 lines. The character configuration is up to 24 dots x 32 dots for high resolution, ideal for wide-screen TV, HDTV, and high-resolution personal computer displays. The character display functions include sprite character, character background display, and graphics functions, contributing to the use of colorful GUI displays. The MB90096 contains display memory (VRAM), character font ROM, and VCO, allowing characters to be displayed with a minimum of external components. This device also includes command table ROM for storage of display command data, greatly reducing the load on the microcontroller. s PACKAGES 28-pin plastic SH-DIP 28-pin plastic SOP (DIP-28P-M03) (FPT-28P-M17) MB90096 s FEATURES • Screen display capacity: Up to 32 characters x 16 lines (512 characters) • Character configuration: L size: 24 dots (horizontal) x 2h * dots (vertical) M size: 18 dots (horizontal) x 2h * dots (vertical) S size: 12 dots (horizontal) x 2h * dots (vertical) *: h = 9 to 16 • L, M, S sizes can be selected by individual character • Graphics characters can be displayed in L or S size only • Two h values can be set per screen, and either of the two can be selected for each line on the screen. Font types: 512 different fonts included (user selectable over entire screen) Display modes: Normal characters/graphic characters: (set for each character) Trimmed display (horizontal trimming/pattern back ground): (set for each screen) Character background (fill/shaded background): (set for each character) Line background (fill/shaded back ground): (set for each line) Enlarged (normal, double width, double height, double width x double height): (set for each line) Blinking: Blinking characters: (set for each character) Blink period, duty ratio: (set for each screen) Sprite character display (graphics display only): Capable of displaying one block of characters (maximum 2 x 2 characters) on main screen. (Can move horizontally and vertically in 2-dot increments.) Setting applies to the first 256 characters only (character codes 000 to 0FFH). Background character display (graphics display only): Capable of displaying a repeated pattern (2 x 2 characters) on main screen. Setting applies to the first 256 characters only (character codes 000 to 0FFH). Display colors: Character/background colors: 16 colors each (set for each character) Line background/fill colors: 16 characters each (set for each line) Screen background colors: 16 colors (set for each screen) Graphics character dot colors: 16 colors (set for each dot) Shading background frame colors (highlight/shadow): 16 colors each (set for each screen) Display position control: Horizontal display start position:Set in 4-dot units (for each screen) Vertical display start position: Set in 4-dot units (for each screen) Line spacing control: Set in 2-dot units (for each line) Character/color signal output: ROUT, GOUT, BOUT, IOUT (color signals) VOB1 (OSD display period output signal) VOB2 (semi-transparent color period output signal) Command transfer function (macro service): Command table ROM, 16Kbyte included Compatible horizontal sync signal frequencies: 15 kHz to 120 kHz (PLL circuit included) Microcontroller interface: 16-bit serial input (3 signal input pins) Packages: SH-DIP-28, SOP-28 Power supply voltage: +5 V • • • • • • • • • • • • 2 MB90096 s PIN ASSIGNMENTS (TOP VIEW) CPOUT AVSS VCOIN AVSS RESET TEST VSS DOCKI DOCKO FH EVEN HSYNC VSYNC DISP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AV3V AVCC CS SIN SCLK TRE VCC V3V BOUT (C0) ROUT (C1) GOUT (C2) IOUT (C3) VOB1 VOB2 (DIP-28P-M03) (FPT-28P-M17) 3 MB90096 s PIN DESCRIPTIONS Pin no. 1 3 Pin name CPOUT VCOIN I/O O I Circuit type A B Function Horizontal sync phase comparison result signal output pin. Connects to external low-pass filter. Internal VCO voltage input pin. Receives voltage signal input from external low-pass filter Dot clock input pin. Used only when operating on an externally generated dot clock signal. *1 When unused, the horizontal sync signal *2 should be input at this pin. Internal pull-up resistance included. Output pin for the dot clock signal generated by the internal VCO. This signal can be fixed at “H” level by a command. Output pin for the horizontal sync signal generated by the PLL circuit. Field control signal input pin. This pin is disabled when noninterlaced display or internally generated field control signals are selected by command. Internal pull-up resistance included. Horizontal sync signal input pin. The period of this signal is used to generate the dot clock signal. The active level is programmable. Internal pull-up resistance included. Vertical sync signal input pin. The active level is programmable. Internal pull-up resistance included. Display output (ROUT, GOUT, BOUT, IOUT, VOB1, VOB2) control pin. When this pin is set to “L” level, the display control is forcibly set to inactive. Normally, the horizontal and vertical blanking signals are input here. *3 Internal pull-up resistance included. Color signal output pins. The active level is programmable. Display period output pin. The active level is programmable. Semi-transparent period output signal. The active level is programmable. Serial transfer shift clock input pin. Internal pull-up resistance included. Serial data input pin. Internal pull-up resistance included. Chip select pin. Set to “L” level for serial transfer. Internal pull-up resistance included. 8 DOCKI I D 9 10 DOCKO FH O O C C 11 EVEN I D 12 HSYNC I D 13 VSYNC I D 14 DISP I D 17 18 19 20 16 15 24 25 IOUT (C3) GOUT (C2) ROUT (C1) BOUT (C0) VOB1 VOB2 SCLK SIN O C O O I I C C D D 26 CS I D (Continued) 4 MB90096 (Continued) Pin Pin name no. 23 5 TRE RESET I/O O I Circuit type C D Function Output pin for indicator that command transfer and fill operations are in progress. Active “H” level output. Reset input pin. Input a “L” level signal *4 at power-on. Internal pull-up resistance included. Test signal input pin. Input “H” level (fixed) for normal operation. Internal pull-up resistance included. +5 V power supply pin. Connect 0.1 µF capacitance between this pin and VSS. Ground pin. +5 V power supply pin for VCO. Connect 0.1 µF capacitance between this pin and AVSS. Ground pin for VCO. 6 22 21 7 27 28 2, 4 TEST VCC V3V VSS AVCC AV3V AVSS I       D       *1: The clock signal should be input even during a reset interval. *2: The active level of the horizontal sync signal input may be either “H” or “L” level. During reset intervals, including power-on resets, apply a “L” level fixed signal or a horizontal sync signal with one or more “L” level intervals at the DOCKI pin. *3: The MB90096 display signals (IOUT, ROUT, GOUT, BOUT, VOB1, VOB2) may be output during horizontal or vertical blanking intervals. Normally devices such as TV or monitors use a reverence color setting during horizontal and vertical blanking intervals, so that during this period the MB90096 display signals must be masked at the DISP pin signal. *4: When power is switched on, apply a “L” level signal for 1ms or longer after the VCC (AVCC) is stabilized. 5 MB90096 s I/O CIRCUIT TYPES Type Circuit (internal 3 V) Pch Remarks • CMOS output (internal 3 V) 3-state output A Nch • Analog input Nch Pch B (5 V) Pch • CMOS output (5 V) C Nch (5 V) • CMOS hysteresis input Pull-up resistance (approx. 50 kΩ) included D 6 MB90096 s BLOCK DIAGRAM DISP VSYNC EVEN RESET BOUT ROUT Display control CS SIN SCLK Serial input control Display output control GOUT IOUT VOB1 VOB2 TRE Command table ROM control Display memory VRAM Font ROM (512 char.) (32 char. x 16 line) Command table ROM Dot clock (16 KByte) DOCKI HSYNC CPOUT VCOIN Dot clock generator circuit (PLL circuit) FH DOCKO 7 MB90096 s ABSOLUTE MAXIMUM RATINGS (VSS = AVSS = 0 V Typ) Parameter Power supply voltage Capacitance pins Input voltage Output voltage Power consumption Operating temperature Storage temperature Symbol VCC AVCC V3V, AV3V VIN VOUT Pd Ta Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3  −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 3.6 VCC + 0.3 VCC + 0.3 600 +85 +150 Unit V V V V V mW °C °C * * Remarks *: AVcc and Vcc must have equal potential. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS (VSS = AVSS = 0 V Typ) Parameter Power supply voltage “H” level input voltage “L” level input voltage Operating temperature Analog input voltage Smoothing capacitor (capacitance pin) Value Symbol Min VCC AVCC VIHS VILS2 Ta VIN CS 4.5 4.5 Max 5.5 5.5 Unit Remarks Specification guarantee range *1 V V V V °C V 0.8 × VCC VCC + 0.3 VSS − 0.3 0.2 × VCC −40 0 0.1 +85 3.0 1.0 VCOIN input *2 Use a ceramic capacitor or other capacitor having µF equivalent frequency characteristics. The capacitance at the Vcc and AVcc pins must be greater than Cs. *1: AVcc and Vcc must have equal potential. *2: This recommended input voltage range does not imply that stable PLL operation is warranted. For stable PLL operation it is recommended that input voltage be between 1.0 V and 2.5 V. Note however that PLL operating status is greatly affected by variations in the input horizontal sync signal period, as well as external filter settings and operating temperature, etc. Thorough testing and eva