128M (X16) FLASH MEMORY 32M (X16) Mobile FCRAMTM

www.DataSheet4U.com SPANSION MCP Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-50225-2E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 128M (×16) FLASH MEMORY & 32M (×16) Mobile FCRAMTM MB84VP24491HK-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 20 ns maximum page read access time, 70 ns maximum random access time (Flash) 20 ns maximum page read access time, 70 ns maximum random access time (FCRAM) • Operating Temperature –30 °C to +85 °C • Package 73-ball FBGA (Continued) s PRODUCT LINEUP Flash Supply Voltage (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 3.0 V 70 20 70 20 +0.1V –0.3 V FCRAM VCCr* = 3.0 V +0.1V –0.3 V 70 20 70 40 *: Both VCCf and VCCr must be the same level when either part is being accessed. s PACKAGE 73-ball plastic FBGA (BGA-73P-M03) MB84VP24491HK-70 (Continued) — FLASH MEMORY • 0.13 µm Process Technology • Dual Chip Enable (CE0f, CE1f) CE0f controls 64M bits (Bank A and Bank B) region and CE1f controls 64M bits (Bank C and Bank D) bits region. • Single 3.0 V Read, Program and Ease Minimized system level power requirements • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM *1 Bank A(CE0f): 16 Mbit (4 KW ×8 and 32 KW ×31) Bank B(CE0f): 48 Mbit (32 KW ×96) Bank C(CE1f): 48 Mbit (32 KW ×96) Bank D(CE1f): 16 Mbit (4 KW ×8 and 32 KW ×31) • High Performance Page Mode 20 ns maximum page access time (70 ns random access time) • 8 words Page Access Capability • Minimum 100,000 Program/Erase Cycles • Sector Erase Architecture Eight 4 Kwords, two hundred fifty-four 32 Kwords, eight 8 Kwords sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase • Dual Boot Block Sixteen 4Kwords boot block sectors, eight at the top of the address range and eight at the bottom of the address range • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode • Low VCC Write Inhibit ≤ 2.5 V • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data (Continued) 2 MB84VP24491HK-70 (Continued) • New Sector Protection Persistent Sector Protection Password Sector Protection • Please refer to “MBM29RM12DH” Datasheet in detailed function — FCRAMTM *3 • Power Dissipation Operating : 30 mA Max Standby : 100 µA Max • Power Down Mode Sleep : 10 µA Max 4M Partial : 45 µA Max 8M Partial : 55 µA Max 16M Partial: 70 µA Max • Power Down Control by CE2r • Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) • 8 words Page Access Capability *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan. 3 MB84VP24491HK-70 s PIN ASSIGNMENT (Top View) Marking Side A10 N.C. B10 N.C. D9 A15 C8 A11 C7 A8 B6 N.C. B5 N.C. C6 WE C5 WP/ACC C4 LB C3 A7 D8 A12 D7 A19 D6 CE2r D5 RESET D4 UB D3 A6 D2 A3 E9 A21 E8 A13 E7 A9 E6 A20 E5 RY/BY E4 A18 E3 A5 E2 A2 F10 N.C. F9 CE1f F8 A14 F7 A10 G10 N.C. G9 A16 G8 N.C. G7 DQ6 H9 N. C. H8 DQ15 H7 DQ13 H6 DQ4 H5 DQ3 J9 VSS J8 DQ7 J7 DQ12 J6 VCCr J5 VCCf J4 DQ10 J3 DQ0 J2 CE1r K8 DQ14 K7 DQ5 K6 N.C. K5 DQ11 K4 DQ2 K3 DQ8 L10 N.C. M10 N.C. L6 N.C. L5 N.C. F4 A17 F3 A4 F2 A1 F1 N.C. G4 DQ1 G3 VSS G2 A0 G1 N.C. H4 DQ9 H3 OE H2 CE0f A1 N.C. B1 N.C. C1 N.C. L1 N.C. M1 N.C. (BGA-73P-M03) 4 MB84VP24491HK-70 s PIN DESCRIPTION Pin name A20 to A0 A21 DQ15 to DQ0 CE0f CE1f CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCr Input/ Output I I I/O I I I I I I O I I I I — Power Power Power Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Description 5 MB84VP24491HK-70 s BLOCK DIAGRAM VCCf A21 to A0 A21 to A0 WP/ACC RESET CE0f CE1f 128 M bit Flash Memory (Dual CE) VSS RY/BY DQ15 to DQ0 DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 VSS LB UB WE OE CE1r CE2r 32 M bit FCRAM 6 MB84VP24491HK-70 s DEVICE BUS OPERATIONS Operation*1, *2 Full Standby CE0f CE1f CE1r CE2r OE WE LB H H Output Disable* 3 UB X A21 to A0 X X* 8 DQ7 to DQ0 High-Z WP/ DQ15 to RESET ACC DQ8 *9 High-Z H X H H H L H L H L H L H H H H H H X X X L H H H H X X X High-Z High-Z H X Read from Flash*4 L H L H H H H L H H H L L X X X L X X X L L H H L L H H X X X X Valid Valid Valid DOUT DIN DIN DIN DOUT DIN DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X H H H X X X Write to Flash Read from FCRAM H H L H L H H L Valid High-Z DIN H X FCRAM No Read H H L H L H H L Valid High-Z DIN H X Write to FCRAM H H L H H* 7 L H L Valid High-Z DIN H X FCRAM No Write Flash Temporary Sector Group Unprotection*5 Flash Hardware Reset Flash Boot Block Sector Write Protection FCRAM Power Down*6 H X X X X H X X X X L X H X X H X H X L H* X X X X 7 L X X X X H X X X X Valid X X X X High-Z X High-Z X X H VID L X X X X X L X Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See sDC CHARACTERISTICS for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : Do not apply for two or more states of the following conditions at the same time; • CE0f = VIL • CE1f = VIL • CE1r = VIL and CE2r = VIH *3 : Should not be kept FCRAM Output Disable condition longer than 1µs. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : It is also used for the extended sector group protections. *6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program” in FCRAM Characteristics part. *7 : OE can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous operation cycle is satisfied. 2) OE stays VIL during Write cycle. *8 : Can be either VIL or VIH but must be valid before Read or Write. *9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors. 7 MB84VP24491HK-70 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCr Supply *1 RESET *2 WP/ACC *3 Symbol Tstg TA VIN, VOUT VCCf, VCCr VIN VIN Rating Min –55 –30 –0.3 –0.3 –0.5 –0.5 Max +125 +85 VCCf +0.3 VCCr +0.3 +3.3 + 13.0 +10.5 Unit °C °C V V V V V *1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN – VCCf) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf