64M (X16) Page FLASH MEMORY & 32M (X16) Mobile FCRAMTM

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-50224-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64M (×16) Page FLASH MEMORY & 32M (×16) Mobile FCRAMTM MB84VP23481FK-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 25 ns maximum page read access time, 65 ns maximum random access time (Flash) 20 ns maximum page read access time, 70 ns maximum random access time (FCRAM) • Operating Temperature –30 °C to +85 °C • Package 65-ball FBGA (Continued) s PRODUCT LINEUP Flash Supply Voltage (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 3.0 V 65 25 65 25 +0.1V –0.3 V FCRAM VCCr* = 3.0 V –0.3 V 70 20 70 40 +0.1V *: Both VCCf and VCCr must be the same level when either part is being accessed. s PACKAGE 65-ball plastic FBGA (BGA-65P-M01) MB84VP23481FK-70 (Continued) — FLASH MEMORY • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM *1 Bank A: 8 Mbit (8 KB ×8 and 64 KB ×15) Bank B: 24 Mbit (64 KB ×48) Bank C: 24 Mbit (64 KB ×48) Bank D: 8 Mbit (8 KB ×8 and 64 KB ×15) • 8 words Page • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Minimum 100,000 Program/Erase Cycles • Sector Erase Architecture Eight 8 Kbytes, a hundred twenty-six 64 Kbytes, eight 8 Kbytes sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase • Dual Boot Block Sixteen to 8Kbytes boot block sectors, eight at the top of the address range and eight at the bottom of the address range • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • New Sector Protection Persistent Sector Protection Password Sector Protection • Please refer to “MBM29QM64DF” Datasheet in Detailed Function (Continued) 2 MB84VP23481FK-70 (Continued) — FCRAMTM *3 • Power Dissipation Operating : 30 mA Max Standby : 100 µA Max • Power Down Mode Sleep : 10 µA Max 4M Partial : 45 µA Max 8M Partial : 55 µA Max 16M Partial: 70 µA Max • Power Down Control by CE2r • Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) • 8 words Page Access Capability *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan. 3 MB84VP23481FK-70 s PIN ASSIGNMENT (Top View) Marking Side A10 N.C. A9 N.C. B8 A11 B7 A8 B6 WE B5 WP/ACC B4 LB B3 A7 A2 N.C. A1 N.C. B1 N.C. C9 A15 C8 A12 C7 A19 C6 CE2r C5 RESET C4 UB C3 A6 C2 A3 D9 A21 D8 A13 D7 A9 D6 A20 D5 RY/BY D4 A18 D3 A5 D2 A2 E4 A17 E3 A4 E2 A1 F4 DQ1 F3 VSS F2 A0 E9 N.C. E8 A14 E7 A10 F9 A16 F8 N.C F7 DQ6 G9 N.C G8 DQ15 G7 DQ13 G6 DQ4 G5 DQ3 G4 DQ9 G3 OE G2 CEf H9 Vss H8 DQ7 H7 DQ12 H6 Vccr H5 Vccf H4 DQ10 H3 DQ0 H2 CE1r J8 DQ14 J7 DQ5 J6 N.C J5 DQ11 J4 DQ2 J3 DQ8 K10 N.C. K9 N.C. K2 N.C. K1 N.C. (BGA-65P-M01) 4 MB84VP23481FK-70 s PIN DESCRIPTION Pin name A20 to A0 A21 DQ15 to DQ0 CEf CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCr Input/ Output I I I/O I I I I I O I I I I — Power Power Power Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Description 5 MB84VP23481FK-70 s BLOCK DIAGRAM VCCf A21 to A0 A21 to A0 WP/ACC RESET CEf VSS RY/BY 64 M bit Page Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 LB UB WE OE CE1r CE2r 32 M bit FCRAM VSS 6 MB84VP23481FK-70 s DEVICE BUS OPERATIONS Operation*1, *2 Full Standby Output Disable*3 Read from Flash*4 Write to Flash CEf H H L L L CE1r CE2r OE WE H L H H H H H H H X H L H X H H L LB X X X X L Read from FCRAM H L H L H H L FCRAM No Read H L H L H H L Write to FCRAM H L H H*7 L H L FCRAM No Write Flash Temporary Sector Group Unprotection*5 Flash Hardware Reset Flash Boot Block Sector Write Protection FCRAM Power Down*6 H X X X X L X H X X H X H X L H*7 X X X X L X X X X H X X X X UB X X X X L L H H L L H H X X X X Valid X X X X Valid Valid Valid A21 to A0 X X*8 Valid Valid DQ7 to DQ0 High-Z High-Z DOUT DIN DIN High-Z DIN High-Z DIN High-Z DIN High-Z X High-Z X X DQ15 to RESET WP/ACC*9 DQ8 High-Z High-Z DOUT DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X H VID L X X X X X L X H X H X H X H H H H X X X X Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See sDC CHARACTERISTICS for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : Do not apply for two or more states of the following conditions at the same time; • CEf = VIL • CE1r = VIL and CE2r = VIH *3 : Should not be kept FCRAM Output Disable condition longer than 1µs. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : It is also used for the extended sector group protections. *6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program” in FCRAM Characteristics part. *7 : OE can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous operation cycle is satisfied. 2) OE stays VIL during Write cycle. *8 : Can be either VIL or VIH but must be valid before Read or Write. *9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors. 7 MB84VP23481FK-70 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCr Supply *1 RESET *2 WP/ACC *3 Symbol Tstg TA VIN, VOUT VCCf, VCCr VIN VIN Rating Min –55 –30 –0.3 –0.3 –0.5 –0.5 Max +125 +85 VCCf + 0.3 VCCr + 0.3 +3.3 + 13.0 +10.5 Unit °C °C V V V V V *1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCr Supply Voltages Symbol TA VCCf, VCCr Value Min –30 +2.7 Max +85 +3.1 Unit °C V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 8 MB84VP23481FK-70 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current (Flash) WP/ACC Acceleration Program Current (Flash) Flash VCC Active Current *1,*6 (Initial/Random Read) Flash VCC Active Current *2 Flash VCC Current (Page Mode) *9,*6 Flash VCC Active Current*5,*6 (Read-While-Program) Flash VCC Active Current*5,*6 (Read-While-Erase) Flash VCC Active Current*5,*6 (Erase-Suspend-Program) Flash VCC Current (Standby) *6 Flash VCC Current (Standby, Reset) *6 Flash VCC Current