64 M (X16) FLASH MEMORY & 32 M (X16) Mobile FCRAM

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-50310-2E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64 M (×16) FLASH MEMORY & 32 M (×16) Mobile FCRAMTM MB84VD23481FJ-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (FCRAM) • Operating Temperature −30 °C to +85 °C • Package 65-ball FBGA (Continued) s PRODUCT LINE-UP Flash Memory Power Supply Voltage ( V ) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 2.7 V to 3.1 V 70 70 30 FCRAM VCCr* = 2.7 V to 3.1 V 65 65 40 *: Both VCCf and VCCr must be the same level when either part is being accessed. s PACKAGE 65-ball plastic FBGA (BGA-65P-M01) MB84VD23481FJ-70 (Continued) • FLASH MEMORY • 0.17 µm Process Technology • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM *1 Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15) Bank B : 24 Mbit (64 KB × 48) Bank C : 24 Mbit (64 KB × 48) Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15) Two virtual Banks are chosen from the combination of four physical banks. Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Single 3.0 V Read, Program, and Erase Minimized system level power requirements • Minimum 100,000 Program/Erase Cycles • Sector Erase Architecture Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word. Any combination of sectors can be concurrently erased. It also supports full chip erase. • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector protection/ unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode. • Low VCCf Write Inhibit ≤ 2.5 V • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Please Refer to “MBM29DL64DF” Datasheet in Detailed Function (Continued) 2 MB84VD23481FJ-70 (Continued) • FCRAMTM *3 • Power Dissipation Operating : 25 mA Max Standby : 100 µA Max • Power Down Mode Sleep : 10 µA Max NAP : 60 µA Max 8M Partial : 70 µA Max • Power Down Control by CE2r • Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) • 8 words Address Access Capability *1 : FlexBankTM is a trademark of Fujitsu Limited, Japan. *2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3 : FCRAMTM is a trademark of Fujitsu Limited, Japan. 3 MB84VD23481FJ-70 s PIN ASSIGNMENT FBGA (TOP VIEW) Marking side A10 N.C. A9 N.C. B8 A11 B7 A8 B6 WE B5 WP/ACC B4 LB B3 A7 A2 N.C. A1 N.C. B1 N.C. C9 A15 C8 A12 C7 A19 C6 CE2r C5 RESET C4 UB C3 A6 C2 A3 D9 A21 D8 A13 D7 A9 D6 A20 D5 RY/BY D4 A18 D3 A5 D2 A2 E4 A17 E3 A4 E2 A1 F4 DQ1 F3 VSS F2 A0 E9 N.C. E8 A14 E7 A10 F9 A16 F8 PE F7 DQ6 G9 Vccf G8 DQ15 G7 DQ13 G6 DQ4 G5 DQ3 G4 DQ9 G3 OE G2 CEf H9 Vss H8 DQ7 H7 DQ12 H6 Vccr H5 Vccf H4 DQ10 H3 DQ0 H2 CE1r J8 DQ14 J7 DQ5 J6 N.C. J5 DQ11 J4 DQ2 J3 DQ8 K10 N.C. K9 N.C. K2 N.C. K1 N.C. (BGA-65P-M01) 4 MB84VD23481FJ-70 s PIN DESCRIPTION Pin Name A20 to A0 A21 DQ15 to DQ0 CEf CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC PE N.C. VSS VCCf VCCr Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect/Acceleration (Flash) Partial Enable (FCRAM) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Function Input/Output I I I/O I I I I I O I I I I I  Power Power Power s BLOCK DIAGRAM VCCf A21 to A0 A21 to A0 WP/ACC RESET CEf 64 M bit Flash Memory DQ15 to DQ0 VSS RY/BY DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 VSS PE LB UB WE OE CE1r CE2r 32 M bit FCRAM 5 MB84VD23481FJ-70 s DEVICE BUS OPERATIONS Operation *1,*2 Full Standby Output Disable *3 Read from Flash * Write to Flash Read from FCRAM *5 Write to FCRAM Temporary Sector Group Unprotection*6 Flash Hardware Reset Boot Block Sector Write Protection FCRAM Power Down Program *7 FCRAM No Read FCRAM Power Down *8 4 CEf CE1r CE2r OE WE H H L L L H H L H H H L H H H H H H X H H L H L X H H H L H LB X X X X X L*9 L UB X X X X X L*9 L L H X X X X H X PE A21 to A0 DQ7 to DQ0 H H H H H H X X* 10 DQ15 to RESET DQ8 WP/ ACC*12 High-Z High-Z High-Z DOUT DIN DOUT DIN High-Z High-Z High-Z DOUT DIN DOUT DIN DIN High-Z X High-Z X High-Z High-Z X H H H H H H X X X X X X X Vaild Vaild Vaild H L H H L H L H Vaild High-Z DIN H X X X X H H X X H X H L X X H X H H L X X X X L X X X X X H X X X X X H X X X X L H X X X X KEY*11 Vaild X X High-Z X High-Z High-Z X VID L X H H X X X L X X X Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are prohibited. *2 : Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once. *3 : FCRAM Output Disable condition should not be kept longer than 1 ms. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : FCRAM LB,UB control at Read operation is not supported. *6 : It is also used for the extended sector group protections. *7 : The FCRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re-programmed after regular Read or Write. *8 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention depends on the selection of Power Down Program. *9 : Either or both LB and UB must be Low for FCRAM Read Operation. *10 : Can be either VIL or VIH but must be valid before Read or Write. *11 : See “ FCRAM Power Down Program Key Table “. *12 : Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors. 6 MB84VD23481FJ-70 s 64M FRASH MEMORY CHARACTERISTICS for MCP 1. FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY • Sixteen 4K words, and one hundred twenty-six 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. Word Mode 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh Word Mode 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh Bank A Bank B SA0 : 8KB (4KW) SA1 : 8KB (4KW) SA2 : 8KB (4KW) SA3 : 8KB (4KW) SA4 : 8KB (4KW) SA5 : 8KB (4KW) SA6 : 8KB (4KW) SA7 : 8KB (4KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 64KB (32KW) SA32 : 64KB (32KW) SA33 : 64KB (32KW) SA34 : 64KB (32KW) SA35 : 64KB (32KW) SA36 : 64KB (32KW) SA37 : 64KB (32KW) SA38 : 64KB (32KW) SA39 : 64KB (32KW) SA40 : 64KB (32KW) SA41 : 64KB (32KW) SA42 : 64KB (32KW) SA43 : 64KB (32KW) SA44 : 64KB (32KW) SA45 : 64KB (32KW) SA46 : 64KB (32KW) SA47 : 64KB (32KW) SA48 : 64KB (32KW) SA49 : 64KB (32KW) SA50 : 64KB (32KW) SA51 : 64KB (32KW) SA52 : 64KB (32KW) SA53 : 64KB (32KW) SA54 : 64KB (32KW) SA55 : 64KB (32KW) SA56 : 64KB (32KW) SA57 : 64KB (32KW) SA58 : 64KB (32KW) SA59 : 64KB (32KW) SA60 : 64KB (32KW) SA61 : 64KB (32KW) SA62 : 64KB (32KW) SA63 : 64KB (32KW) SA64 : 64KB (32KW) SA65 : 64KB (32KW) SA66 : 64KB (32KW) SA67 : 64KB (32KW) SA68 : 64KB (32KW) SA69 : 64KB (32KW) SA70 : 64KB (32KW) Bank C Bank D SA71 : 64KB (32KW) SA72 : 64KB (32KW) SA73 : 64KB (32KW) SA74 : 64KB (32KW) SA75 : 64KB (32KW) SA76 : 64KB (32KW) SA77 : 64KB (32KW) SA78 : 64KB (32KW) SA79 : 64KB (32KW) SA80 : 64KB (32KW) SA81 : 64KB (32KW) SA82 : 64KB (32KW) SA83 : 64KB (32KW) SA84 : 64KB (32KW) SA85 : 64KB (32KW)