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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50308-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
32M (×16) FLASH MEMORY & 8M (×16) STATIC RAM
MB84VD22280FA-70/MB84VD22290FA-70 MB84VD22280FE-70/MB84VD22290FE-70
s FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V • High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) • Operating Temperature –30°C to +85°C ° ° • Package 59-ball FBGA
(Continued)
s PRODUCT LINE UP
Part No. Supply Voltage(V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MB84VD22280FA/80FE/90FA/90FE VCCf= 3.0 V 70 70 30
+0.1 V –0.3 V
VCCs= 3.0 V 70 70 35
+0.1 V –0.3 V
Note: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
s PACKAGE
59-ball plastic FBGA
(BGA-59P-M02)
MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
(Continued) — FLASH MEMORY • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM*1 Bank A : 4 Mbit (8 KB × 8 and 64 KB × 7) Bank B : 12 Mbit (64 KB × 24) Bank C : 12 Mbit (64 KB × 24) Bank D : 4 Mbit (64 KB × 8) Two virtual Banks are chosen from the combination of four physical banks Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Minimum 100,000 Write/Erase Cycles • Sector Erase Architecture Eight 4K word and sixty-three 32K word sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD22280: Top sector MB84VD22290: Bottom sector • Embedded EraseTM*2 Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCCf Write Inhibit ≤ 2.5 V • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, increases program performance • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to “MBM29DL32TF/BF” Datasheet in Detailed Function — SRAM • Power Dissipation Operating: 50 mA Max Standby: 15 µA Max • Power Down Features using CE1s and CE2s • Data Retention Supply Voltage: 1.5 V to 3.1 V • CE1s and CE2s Chip Select • Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
*1 : FlexBankTM is a trademark of Fujitsu Limited, Japan. *2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2
MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s PIN ASSIGNMENT
(Top View) Marking side
A8 N.C. B7 A11 B6 A8 B5 WE B4
C8 A15 C7 A12 C6 A19 C5 CE2s C4
D8 N.C. D7 A13 D6 A9 D5 A20 D4 RY/BY D3 A18 D2 A5 D1 A2
E8 N.C. E7 A14 E6 A10
F8 A16 F7 N.C. F6 DQ6
G8 N.C. G7 DQ15 G6 DQ13 G5 DQ4 G4 DQ3
H8 Vss H7 DQ7 H6 DQ12 H5 Vccs H4 Vccf H3 DQ10 H2 DQ0 H1 CE1s J7 DQ14 J6 DQ5 J5 N.C. J4 DQ11 J3 DQ2 J2 DQ8
K8 N.C.
WP/ACC RESET B3 LB B2 A7 C3 UB C2 A6 C1 A3
E3 A17 E2 A4 E1 A1
F3 DQ1 F2 VSS F1 A0
G3 DQ9 G2 OE G1 CEf
K1 N.C.
(BGA-59P-M02)
3
MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s PIN DESCRIPTION
Pin Name A18 to A0 A20, A19 DQ15 to DQ0 CEf CE1s CE2s OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCs Function Address Inputs (Common) Address Input (Flash) Data Inputs / Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin / Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Input/Output I I I/O I I I I I O I I I I — Power Power Power
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MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s BLOCK DIAGRAM
VCCf A20 to A0 A20 to A0 VSS RY/BY
WP/ACC RESET CEf
32 M bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCs A18 to A0 DQ15 to DQ0 VSS
LB UB WE OE CE1s CE2s
8 M bit Static RAM
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MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s DEVICE BUS OPERATIONS
• User Bus Operations Operation *1,*3 Full Standby CEf CE1s CE2s OE H H X L H X H X H X X L H X L X L X L X H X H WE X H X H LB X X H X UB X X H X DQ7 to DQ0 DQ15 to DQ8 RESET High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H X H WP/ ACC*5 X
H Output Disable L
Read from Flash *2
L
L
H
X
X
DOUT
DOUT
H
X
Write to Flash
L
H
L
X L
X L L H L L H X X
DIN DOUT High-Z DOUT DIN High-Z DIN X High-Z
DIN DOUT DOUT High-Z DIN DIN High-Z X High-Z X
H
X
Read from SRAM
H
L
H
L
H
H L L
H
X
Write to SRAM
H
L
H
X
L
H L
H
X
Temporary Sector Group Unprotection *4 Flash Hardware Reset
X X
X H X
X X L
X X
X X
X X
VID L X
X X L
Boot Block Sector Write X X X X X X X X Protection Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%.
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MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCs Supply *1 RESET *
2 3
Symbol Tstg TA VIN, VOUT VCCf,VCCs VIN VIN
Rating Min –55 –30 –0.3 –0.3 –0.5 –0.5 Max +125 +85 VCCf + 0.3 VCCs + 0.4 +3.3 +13.0 +10.5
Unit °C °C V V V V V
WP/ACC *
*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+1.0 V or VCCs+1.0 V for periods of up to 20 ns. *2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol TA Vccf, Vccs Value Min –30 +2.7 Max +85 +3.1 Unit °C V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB84VD22280FA/FE-70/MB84VD22290FA/FE-70
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Flash VCC Active Current (Read) *1 Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program) *5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) ACC Input Leakage Current SRAM VCC Active Current
Symbol
Test Conditions VIN = VSS to VCCf, VCCs VOUT = VSS to VCCf, VCCs VCCf = VCCf Max, VCCs = VCCs Max, RESET = 12.5 V CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCf = VCCf Max, VCCs = VCCs Max, WP/ACC = VACC Max VCCs = VCCs Max, CE1s = VIL, CE2s = VIH tCYCLE = 10 MHz tCYCLE = 5 MHz tCYCLE = 1 MHz
Value Min –1.0 –1.0 — — — — — — — — Typ — — — — — — — — — — Max +1.0 +1.0 35 18 4 25 43 43 25 20
Unit µA µA µA mA mA mA mA mA mA mA
ILI ILO ILIT ICC1f ICC2f ICC3f ICC4f ICC5f ILIA
ICC1s
— — — —
— — — —
50 50 10 5
mA mA mA µA µA
SRAM VCC Active Current
ICC2s
tCYCLE = 10 MHz CE1s = 0.2 V, CE2s = VCCs – 0.2 V tCYCLE = 1 MHz VCCf = VCCf Max, CEf = VCCf ± 0.3 V, RESET = VCCf ± 0.3 V, WP/ACC = VCCf± 0.3 V VCCf = VCCf Max, RESET = VSS ± 0.3 V, WP/ACC = VCCf± 0.3 V VCCf = VCCf Max, CEf = VSS ± 0.3 V, RESET = VCCf ± 0.3 V, WP/ACC = VCCf± 0.3 V, VIN = VCCf± 0.3 V o
