ASSP Single Serial Input PLL Frequency Synthesizer On-Chip 2.0GHz Prescaler

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-21330-1E ASSP Single Serial Input PLL Frequency Synthesizer On-Chip 2.0GHz Prescaler MB15E05 s DESCRIPTION The Fujitsu MB15E05 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.0 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6mA typ. This operates with a supply voltage of 3.0V (typ.). Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of this, MB15E05 is ideally suitable for digital mobile communications, such as PCN (Personal Communication Network), PCS (Personal Communication Service), etc. s FEATURES • • • • • • • High frequency operation: 2.0 GHz max Low power supply voltage: VCC = 2.7 to 3.6V Very Low power supply current : ICC = 6.0 mA typ. (Vcc = 3V) Power saving function : IPS = 10 µA max. Pulse swallow function: 64/65 or 128/129 Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 • Wide operating temperature: Ta = –40 to 85°C • Plastic 16-pin SSOP package (FPT-16P-M05) s PACKAGE 16-pin, Plastic SSOP (FPT-16P-M05) This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1 MB15E05 s PIN ASSIGNMENT OSCin OSCout Vp Vcc Do GND Xfin fin 1 2 3 4 16 15 14 φR φP LD/fout ZC PS LE Data Clock TOP 13 VIEW 5 12 6 7 8 11 10 9 2 MB15E05 s PIN DESCRIPTIONS Pin No. 1 Pin Name OSCIN I/O I Descriptions Programmable reference divider input. Oscillator input. Connection for an crystal or a TCXO. TCXO should be connected with a coupling capacitor. Oscillator output. Connection for an external crystal. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be reversed by FC input. Ground. Prescaler complementary input, and should be grounded via a capacitor. Prescaler input. Connection with an external VCO should be done with AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = ”H” ; Data is transmitted to the programmable reference counter. Control bit = ”L” ; Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving control input. This pin should be set at ”L” at Power-ON. (Open is prohibited.) PS = ”H” ; Normal mode PS = ”L” ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = ”H” ; Normal Do output. ZC = ”L” ; Do becomes high impedance. Lock detect signal output(LD)/ phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS = ”H” ; outputs fout (fr/fp monitoring output) LDS = ”L” ; outputs LD (”H” at locking, ”L” at unlocking.) Phase comparator output for an external charge pump. Phase comparator output for an external charge pump. 2 3 4 5 6 7 8 9 OSCOUT VP VCC DO GND Xfin fin Clock O – – O – I I I 10 Data I 11 LE I 12 PS I 13 ZC I 14 LD/fout φP φR O 15 16 O O 3 MB15E05 s BLOCK DIAGRAM 1 OSCIN 1 fr Crystal Oscillator circuit OSCOUT 2 fp Programmable reference divider Binary 14-bit reference counter fr LD Phase comparator 16 φR 15 φP Lock detector PS 12 Intermittent mode control (power save) LE SW LDS 17-bit latch FC 14-bit latch 1-bit control latch 3-bit latch fp LD/fr/fp selector 14 LD/fout LE 11 19-bit shift register Data 10 C N T 19-bit shift register Charge pump 13 ZC 3 VP Clock 9 Super charger LE 5 DO 18-bit latch 7-bit latch 11-bit latch SW Programmable divider XfIN 7 fIN 8 Prescaler 64/65, 128/129 Binary 7-bit swallow counter Binary 11-bit programmable counter fp GND 6 VCC 4 MD Control Circuit 4 MB15E05 s ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO Tstg Rating –0.5 to +4.0 VCC to +6.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 –55 to +125 Unit V V V V °C Remark Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. s RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min 2.7 VCC GND –40 Typ 3.0 – – – Max 3.6 6.0 VCC +85 Unit V V V °C Remark Notes: To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device. 5 MB15E05 s ELECTRICAL CHARACTERISTICS Parameter Symbol Condition finIF = 2000MHz, fosc = 12MHz Vcc current at PS =”L” and ZC = ”H” min. 500mVp-p 50Ω termination (Refer to the test circuit.) Value Min – Typ 6.0 Max – Unit Power supply current*1 ICC mA µA MHz MHz dBm mVp–p V µA µA µA V V V µA mA mA Power saving current*2 Operating frequency Crystal oscillator operating frequency fin OSCin Input voltage Data, Clock, LE, PS, ZC Data, Clock, LE, PS Input current ZC OSCin φP Output voltage φR, LD/fout Do High impedance cutoff current Do φP φR, LD/fou Output current Ips fin fOSC VfinIF VOSC VIH VIL IIH IIL IIH IIL IIH IIL VOL VOH VOL VDOH VDOL IOFF IOL IOH IOL IDOH Do IDOL – 100 3 –10 500 Vccx0.7 – –1.0 –1.0 –1.0 – – – – – – – – – – – – – – – – – – – – – – –10.0*2 10 2000 40 +2 VCC – Vccx0.3 +1.0 +1.0 +1.0 0 +100 0 0.4 – 0.4 – 0.4 1.1 – –1.0 – – Input sensitivity Pull up input –100 0 –100 Open drain output – Vcc-0.4 – Vcc-0.4 – – Open drain output 1.0 – 1.0 Vcc = 3.0V, Vp = 5V, VDOH = 4.0V Vcc = 3.0V, Vp = 5V, VDOL = 1.0V – mA – 10.0*2 – *1: Conditions ; Vcc = 3.0V, Ta = 25°C, in locking state. *2: Conditions ; Ta = 25°C 6 MB15E05 s FUNCTION DESCRIPTIONS Pulse Swallow Function The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) M : Preset divide ratio of modules prescaler (64 or 128) Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows: Table.1 Control Bit Control bit (CNT) H L Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider) Shift Register Configuration Programmable Reference Counter LSB Data Flow MSB 1 C N T CNT R1 to R14 SW FC LDS 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5 7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 R 12 14 R 13 15 16 17 18 R 14 SW FC LDS : Control bit : Divide ratio setting bit for the programmable reference counter (5 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fout signal select bit [Table. 1] [Table. 2] [Table. 5] [Table. 7] [Table. 6] Note: Start data input with MSB first 7 MB15E05 Programmable Reference Counter LSB Data Flow MSB 1 C N T 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7 9 N 1 10 N 2 11 N 3 12 N 4 13 N 5 14 N 6 15 N 7 16 N 8 17 N 9 18 N 10 19 N 11 CNT : Control bit N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Start data input with MSB first [Table. 1] [Table. 3] [Table. 4] Table2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio (R) 5 6 ⋅ 16383 R 14 0 0 ⋅ 1 R 13 0 0 ⋅ 1 R 12 0 0 ⋅ 1 R 11 0 0 ⋅ 1 R 10 0 0 ⋅ 1 R 9 0 0 ⋅ 1 R 8 0 0 ⋅ 1 R 7 0 0 ⋅ 1 R 6 0 0 ⋅ 1 R 5 0 0 ⋅ 1 R 4 0 0 ⋅ 1 R 3 1 1 ⋅ 1 R 2 0 1 ⋅ 1 R 1 1 0 ⋅ 1 Note: • Divide ratio less than 5 is prohibited. Table.3 Binary 11-bit Programmable Counter Data Setting Divide ratio (N) 5 6 ⋅ 2047 N 11 0 0 ⋅ 1 N 10 0 0 ⋅ 1 N 9 0 0 ⋅ 1 N 8 0 0 ⋅ 1 N 7 0 0 ⋅ 1 N 6 0 0 ⋅ 1 N 5 0 0 ⋅ 1 N 4 0 0 ⋅ 1 N 3 1 1 ⋅ 1 N 2 0 1 ⋅ 1 N 1 1 0 ⋅ 1 Note: • Divide ratio less than 5 is prohibited. • Divide ratio (N) range = 5 to 2,047 8 MB15E05 Table.4 Binary 7-bit Swallow Counter Data Setting Divide ratio (A) 0 1 ⋅ 127 A 7 0 0 ⋅ 1 A 6 0 0 ⋅ 1 A 5 0 0 ⋅ 1 A