Programmable Logic Device Family

www.DataSheet4U.com MAX 3000A ® Programmable Logic Device Family Data Sheet June 2006, ver. 3.5 Features... ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming High–density PLDs ranging from 600 to 10,000 usable gates 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages Hot–socketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance Industrial temperature range Table 1. MAX 3000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tCO1 (ns) fCNT (MHz) Altera Corporation DS-MAX3000A-3.5 EPM3032A 600 32 2 34 4.5 2.9 3.0 227.3 EPM3064A 1,250 64 4 66 4.5 2.8 3.1 222.2 EPM3128A 2,500 128 8 98 5.0 3.3 3.4 192.3 EPM3256A 5,000 256 16 161 7.5 5.2 4.8 126.6 EPM3512A 10,000 512 32 208 7.5 5.6 4.7 116.3 1 MAX 3000A Programmable Logic Device Family Data Sheet ...and More Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PCI compatible Bus–friendly architecture including programmable slew–rate control Open–drain output option Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power–saving mode for a power reduction of over 50% in each macrocell Configurable expander product–term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs Enhanced architectural features, including: – 6 or 10 pin– or logic–driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Programmable output slew–rate control Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) General Description MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM–based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the –4, –5, –6, –7, and –10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. 2 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 2. MAX 3000A Speed Grades Device –4 EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Speed Grade –5 –6 –7 v v v v v v –10 v v v v v v v The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. Table 3. MAX 3000A Maximum User I/O Pins Device 44–Pin PLCC 34 34 Note (1) 44–Pin TQFP 34 34 100–Pin 144–Pin 208–Pin 256-Pin TQFP TQFP PQFP FineLine BGA 66 80 96 116 158 172 98 161 208 EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Note: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in–system programming or boundary–scan testing, four I/O pins become JTAG pins. MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user–configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. Altera Corporation 3 MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and high–speed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speed–critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non–speed–critical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed–voltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry–standard PC– and UNIX–workstation–based EDA tools. The software runs on Windows–based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f Functional Description For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. The MAX 3000A architecture includes the following elements: ■ ■ ■ ■ ■ Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I/O control blocks The MAX 3000A architecture includes four dedicated inputs that can be used as general–purpose inputs or as high–speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices. 4 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 1. MAX 3000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 or 10 Output Enables (1) LAB A I/O Control Block 2 to 16 Macrocells 1 to 16 36 36 6 or 10 Output Enables (1) LAB B Macrocells 17 to 32 2 to 16 I/O Control Block 2 to 16 I/O 2 to 16 I/O 16 16 2 to 16 PIA LAB D 36 Macrocells 49 to 64 2 to 16 I/O Control Block 6 or 10 6 or 10 LAB C I/O Control Block 2 to 16 Macrocells 33 to 48 2 to 16 36 2 to 16 I/O 2 to 16 I/O 16 16 2 to 16 6 or 10 6 or 10 2 to 16 Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Logic Array Blocks The MAX 3000A device architecture is based on the linking of high–performance LABs. LABs consist of 16–macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ ■ 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Altera Corporation 5 MAX 3000A Programmable Logic Device Family Data Sheet Macrocells MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Figure 2 shows a MAX 3000A macrocell. Figure 2. MAX 3000A Macrocell LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 Programmable Register Register Bypass To I/O Control Block PRN D/T Q Pro