PC133/PC100 Unbuffered DIMM

www.DataSheet4U.com M366S6453CTS M366S6453CTS SDRAM DIMM PC133/PC100 Unbuffered DIMM 64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M366S6453CTS is a 64M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S6453CTS consists of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S6453CTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE • Performance range Part No. M366S6453CTS-L7C/C7C M366S6453CTS-L7A/C7A M366S6453CTS-L1H/C1H M366S6453CTS-L1L/C1L • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,375mil), double sided component • • • • Max Freq. (Speed) 133MHz@CL=2/3 133MHz@CL=3/100MHz@CL=2 100MHz @ CL=2/3 100MHz @ CL=3 PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC *WP **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 72 44 DU 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 52 *CB2 80 53 *CB3 81 82 54 VSS 55 DQ16 83 56 DQ17 84 PIN NAMES Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK3 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 *WP DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Write protection Don′t use No connection CKE0 ~ CKE1 Clock enable input * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 0.0 Sept. 2001 M366S6453CTS PIN CONFIGURATION DESCRIPTION Pin CLK CS Name System clock Chip select PC133/PC100 Unbuffered DIMM Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. CKE Clock enable A0 ~ A12 BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 VDD/VSS Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground REV. 0.0 Sept. 2001 M366S6453CTS FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10Ω DQn VDD Vss • • • • Two 0.1uF Capacitors per each SDRAM To all SDRAMs Every DQpin of SDRAM • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • PC133/PC100 Unbuffered DIMM DQM4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 CS CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U0 U8 U4 U12 U1 U9 DQM CS DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 U13 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS CS DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U2 U10 U6 U14 CS CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 U11 U7 U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U7 CKE1 • 10KΩ SDRAM U8 ~ U15 • • • • 1.5pF U0/U1/U2/U3 U4/U5/U6/U7 U8/U9/U10/U11 U12/U13/U14/U15 VDD Serial PD SCL 47KΩ WP A0 A1 A2 SDA SA0 SA1 SA2 10Ω CLK0/1/2/3 REV. 0.0 Sept. 2001 M366S6453CTS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS PC133/PC100 Unbuffered DIMM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 16 50 Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Pin Symbol CADD CIN CCKE CCLK CCS CDQM COUT Min 80 80 50 40 25 15 10 Max 100 100 60 45 35 20 15 Unit pF pF pF pF pF pF pF Address (A0 ~ A12, BA0 ~ BA1) RAS, CAS, WE CKE (CKE0 ~ CKE1) Clock (CLK0 ~ CLK3) CS (CS0, CS2) DQM (DQM0 ~ DQM7) DQ (DQ0 ~ DQ63) REV. 0.0 Sept. 2001 M366S6453CTS DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC = ∞ Test Condition PC133/PC100 Unbuffered DIMM Version -7C -7A 960 -1H 960 -1L 960 Unit Note Operating current (One bank active) Precharge standby current in power-down mode ICC1 1040 mA 1 ICC2P ICC2PS ICC2N 32 32 320 mA Precharge standby current in non power-down mode CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V C L mA 160 96 96 480 mA ICC2NS ICC3P ICC3PS ICC3N Active standby current in power-down mode mA Active standby current in non power-down mode (One bank active) ICC3NS 400 mA Operating current (Burst mode) Refresh current Self refresh current ICC4 1120 1120 1040 1040 mA 1 ICC5 ICC6 2,000 1,840 1,760 1,760 48 24 mA mA mA 2 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)