256 Kbit (32Kb x 8) UV EPROM and OTP EPROM

M27C256B 256 Kbit (32Kb x 8) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 45ns LOW POWER CONSUMPTION: – Active Current 30mA at 5MHz – Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/byte (PRESTO II ALGORITHM) ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 8Dh 28 28 1 1 FDIP28W (F) PDIP28 (B) DESCRIPTION The M27C256Bis a 256 KbitEPROM offeredin the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768 by 8 bits. The FDIP28W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP32, PLCC32 and TSOP28 (8 x 13.4 mm) packages. PLCC32 (C) TSOP28 (N) 8 x 13.4mn Figure 1. Logic Diagram VCC VPP 15 A0-A14 8 Q0-Q7 Table 1. Signal Names A0-A14 Q0-Q7 E G VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Supply Supply Voltage Ground E G M27C256B VSS AI00755B July 1998 1/15 M27C256B Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections AI00756 Q1 Q2 VSS DU Q3 Q4 Q5 AI00757 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M27C256B 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 A6 A5 A4 A3 A2 A1 A0 NC Q0 A7 A12 VPP DU VCC A14 A13 1 32 A8 A9 A11 NC G A10 E Q7 Q6 9 M27C256B 25 17 Warning: NC = Not Connected, DU = Dont’t Use. Figure 2C. TSOP Pin Connections G A11 A9 A8 A13 A14 VCC VPP A12 A7 A6 A5 A4 A3 22 21 28 1 M27C256B 15 14 7 8 AI00614B A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 DEVICE OPERATION The operating modes of the M27C256B are listed in the Operating Modes. A single power supply is requiredin the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C256B has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equalto the delay from E to output (tELQV). Data is available at the output after delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV-tGLQV. Standby Mode The M27C256B has a standby mode which reduces the supplycurrentfrom 30 mA to 100µA. The M27C256B is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. 2/15 M27C256B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage (3) Value –40 to 125 –50 to 125 –65 to 150 –2 to 7 –2 to 7 –2 to 13.5 –2 to 14 Unit °C °C °C V V V V V CC VA9 (2) VPP Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature Note: X = VIH or VIL, VID = 12V ± 0.5V E VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIH VIH VIL VIH X VIL A9 X X X X X X VID VPP VCC VCC VPP VPP VPP VCC VCC Q0 - Q7 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes Table 4. Electronic Signature Identifier Manufacturer’s Code Device Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 0 Q4 0 0 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 8Dh Two Line Output Control BecauseEPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficientuse of thesetwo controllines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. 3/15 M27C256B Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 10ns 0 to 3V 1.5V Standard ≤ 20ns 0.4V to 2.4V 0.8V and 2V Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3kΩ Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. System Considerations The power switching characteristics of Advance CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of this transient current peaks is dependent on the capacitiveand inductiveloading of the deviceat the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 4/15 M27C256B Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS Test Condition 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC – 0.2V VPP = VCC Min Max ±10 ±10 30 1 100 100 Unit µA µA mA mA µA µA V V V V V –0.3 2 IOL = 2.1mA IOH = –1mA IOH = –100µA 3.6 VCC – 0.7 0.8 VCC + 1 0.4 VOL VOH Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C256B Symbol Alt Parameter Test Condition -45 (3) -60 -70 -80 Unit Min Max Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 45 45 25 25 25 0 0 0 Max Min Max Min Max 60 60 30 30 30 0 0 0 70 70 35 30 30 0 0 0 80 80 40 30 30 ns ns ns ns ns ns Notes: 1. VCC must be applied simultaneously with or before V PP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurement conditions. 5/15 M27C256B Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C256B Symbol Alt Parameter Test Condition -90 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) -10 Min Max 100 100 50 0 0 0 30 30 0 0 0 -12 Min Max 120 120 60 40 40 -15/-20/-25 Min Max 150 150 65 0 0 0 50 50 Unit Max 90 90 40 tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 ns ns ns ns ns ns 30 30 tAXQX Notes: 1. VCC must be applied simultaneously with or before V PP and removed simultaneously or after VPP. 2. Sampl