DDR SDRAM

ESMT Revision History Revision 1.3 -Revise operation voltage. (page 5) Revision 1.2 -Changed tWTR from 1 tCK to 2 tCK. Revision 1.1 -Changed absolute max. voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Symbol VIN, VOUT VDD VDDQ Value -0.5 ~ 4.0 -1.0 ~ 4.0 -0.5 ~ 4.0 Unit V V V M13L128168A -Changed operating VDD from 3.135V~3.6V to 3.135V~3.83V -Updated DC current specification Revision 1.0 (21 Oct. 2002) -No “preliminary” on title. -Added M13L128168A-3.6T Spec. -Changed VDDQ from 2.5V ± 5% to 2.375V ~ 2.8V Revision 0.4 (26 Sep. 2002) -Changed VDD from 3.3V ± 5% to 3.135V ~ 3.6V -Changed operating temperature from 70 °C to 65 °C Revision 0.3 (11 Jul. 2002) -Added DC Current Spec Revision 0.2 (29 May. 2002) -Independent of M13S128168A Revision 0.1 (3 May. 2002) -Original www.DataSheet4U.com Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 1/48 ESMT DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE LDM/UDM for write masking only VDD = 3.135V-3.83V, VDDQ = 2.375V-2.8V Auto & Self refresh 15.6us refresh interval 1 DQS per byte (LDQS, UDQS) SSTL-2 I/O interface 66pin TSOPII package www.DataSheet4U.com M13L128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM ORDERING INFORMATION: PRODUCT NO. M13L128168A-3.6T M13L128168A-4T M13L128168A-5T M13L128168A-6T MAX. FREQ 276MHz 250MHz 200MHz 166MHz 3.3V TSOP II VDD PACKAGE Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 2/48 ESMT Functional Block Diagram CLK CLK CKE Address Mode Register & Extended Mode Register M13L128168A Clock Generator Bank D Bank C Bank B Row Decoder Row Address Buffer & Refresh Counter Bank A Sense Amplifier Control Logic CS RAS CAS WE Command Decoder Data Control Circuit Input & Output Buffer Latch Circuit Column Address Buffer & Refresh Counter DM Column Decoder DQ CLK, CLK DLL DQS DQS Pin Arrangement x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 www.DataSheet4U.com x16 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH) Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 3/48 ESMT (M13L128168A) Pin Name Function Address inputs -Row address A0~A11 -Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe. LDQS corresponds to the data on DQ0~DQ7; UDQS correspond to the data on DQ8~DQ15. Pin Name M13L128168A Function DM is an input mask signal for write data. LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. Clock input Clock enable Chip select Supply Voltage for DQ Ground for DQ Reference Voltage for SSTL-2 No connection A0~A11, BA0,BA1 LDM, UDM DQ0~DQ15 RAS CAS WE VSS VDD LDQS, UDQS CLK, CLK CKE CS VDDQ VSSQ VREF NC www.DataSheet4U.com Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 4/48 ESMT Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note : Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 4.0 -0.5 ~ 4.0 -55 ~ +150 TBD 50 M13L128168A Unit V V V °C W mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 °C ~ 65 °C ) Parameter Supply voltage I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Output High Current (Normal strength driver) (VOUT = VTT+0.76) Output Low Current (Normal strength driver) (VOUT = VTT -0.76 ) Output High Current (Weak strength driver) (VOUT = VTT+0.45) Output Low Current (Weak strength driver) (VOUT = VTT-0.45) Symbol VDD VDDQ VREF www.DataSheet4U.comTT Min 3.135 2.375 0.49*VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 -5 -5 -15.2 +15.2 -9 +9 Max 3.6 2.8 0.51*VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 5 5 Unit V V V V V V V V Note 1 2 V VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ IOH IOL IOH IOL µA µA mA mA mA mA 3 Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF . 3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 5/48 ESMT DC Specifications Parameter Operation Current (One Bank Active) Operation Current (One Bank Active) Precharge Power-down Standby Current Idle Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current Operating Current (Four Bank interleaving) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 Test Condition tRC = tRC (min) tCK = tCK (min) Active - Precharge Burst = 2 tRC = tRC (min), CL=3 IOUT = 0mA, Active-Read-Precharge CKE ≤ VIL(max), tCK = tCK (min), All banks idle -3.6 265 305 65 -4 245 275 60 160 65 160 380 360 620 5 620 M13L128168A Version -5 210 245 55 140 60 140 330 320 510 5 510 -6 180 210 50 120 55 120 300 270 430 5 430 Unit Note mA mA mA mA mA mA mA mA mA mA mA 1 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) 180 All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC = tRAS(max), tCK = tCK (min) Burst=2, CL= 3, tCK = tCK (min), IOUT = 0mA Burst=2, CL= 3, tCK = tCK (min) tRC ≥ tRFC (min) CKE ≤ 0.2V Burst = 4, tRC = tRC (min), CL= 3, IOUT = 0mA, tCK = tCK (min) www.DataSheet4U.com 70 180 410 390 680 5 680 Note 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Input Crossing Point Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.35 VREF - 0.35 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 3.135V~3.83V, VDDQ =2.375V~2.8V, TA = 25 °C , f = 1MHz) Parameter Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data, LDQS and UDQS input/output capacitance Input capacitance (LDM/UDM) Elite Semiconductor Memory Technology Inc. Symbol CIN1 CIN2 COUT CIN3 Min 2.0 2.0 4.0 4.0 Max 4.0 4.0 6.5 6.5 Unit pF pF pF pF Publication Date : Jun. 2003 Revision : 1.3 6/48 ESMT AC Operating Test Conditions (VDD = 3.135V~3.83V, VDDQ =2.375V~2.8V, TA = 0 °C ~65 °C ) Parameter Input reference voltage for clock (VREF) Input signal maximum peak swing Input signal minimum slew rate Input levels (VIH/VIL) Input timing measurement reference level Output timing reference level Value 0.5*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF VTT Unit V V M13L128168A V/ns V V V AC Timing Parameter & Specifications Parameter Clock Period (CL3) (CL2) Access time from CLK/ CLK CLK high-level width CLK low-level width Data strobe edge to clock edge Symbol -3.6 min 3.6 -0.6 0.45 0.45 -0.6 0.75 0.4 0.4 0.75 0.75 0.4 0.4 0.25 0.4 0.9 0.4 0 -0.6 -0.6 +0.6 +0.6 0.6 1.1 0.6 0.6 0.6 0.4 0.25 0.4 0.9 0.4 0 -0.6 -0.6 max 10 +0.6 0.55 0.55 +0.6 1.25 min 4 -0.6 0.45 0.45 -0.6 0.75 0.4 0.4 0.75 0.75 0.4 0.4 -4 max 10 +0.6 0.55 0.55 +0.6 1.25 min 5 -0.7 0.45 0.45 -0.7 0.75 0.45 0.45 0.9 0.9 0.6 0.6 0.4 0.25 0.6 1.1 0.6 0.4 0.9 0.4 0 +0.6 +0.6 -0.7 -0.7 0.4 0.4 -5 max 10 +0.7 0.55 0.55 +0.7 1.25 min 6 -0.75 0.45 0.45 -0.75 0.75 0.5 0.5 1.1 1.1 0.6 0.6 0.45 0.25 0.6 1.1 0.6 0.4 0.9 0.4 0 +0.7 +0.7 -0.75 -0.75 0.4 0.4 -6 max 10 +0.75 0.55 0.55 +0.75 1.25 ns ns ns tCK tCK ns tCK ns ns ns ns 0.6 0.6 0.5 0.6 1.1 0.6 tCK tCK ns tCK tCK tCK tCK ns +0.75 +0.75 ns ns tCK tAC tCH tCL tDQSCK tDQSS tDS tDH tIS tIH tDQSH tDQSL tDQSQ tWPRE tWPST tRPRE tRPST tWPRES tHZ tLZ Clock to first rising edge of DQS delay Data-in an