256 K x 16 DRAM EDO PAGE MODE

www.DataSheet4U.com EliteMT DRAM M11L416256SA 256 K x 16 DRAM EDO PAGE MODE FEATURES X16 organization EDO (Extended Data-Output) access mode 2 CAS Byte/Word Read/Write operation Single 3.3V ( ± 10%) power supply LVTTL-compatible inputs and outputs 512-cycle refresh in 8ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN capabilities Self-refresh capability JEDEC standard pinout Key AC Parameter tRAC -35 35 tCAC 10 tRC 65 tPC 14 ORDERING INFORMATION - PACKAGE 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (Type II) PRODUCT NO. PACKING TYPE COMMENTS M11L416256SASOJ/TSOPII 35 TG M11L416256SA35 JP Pb-free GENERAL DESCRIPTION The M11L416256 series is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers Extended Data-Output , 3.3V( ± 10%) single power supply. Access time (-35) , self-refresh and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device: Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VCC I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VC C TSOP (TypeII) Top View VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O9 I/O8 NC CASL CASH OE A8 A7 A6 A5 A4 VS S VCC I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VC C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O 9 I/O 8 NC CASL CASH OE A8 A7 A6 A5 A4 VS S Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 1/16 www.DataSheet4U.com EliteMT FUNCTIONAL BLOCK DIAGRAM M11L416256SA WE RAS CASL CASH CONTROL LOGIC DATA-IN BUFFER 16 IO0 : IO15 CLOCK GENERATOR DATA-OUT BUFFER 9 COLUMN DECODER 512 16 OE 16 9 A0 A1 A2 A3 COLUMN ADDRESS BUFFER REFRESH CONTROLER SENSE AMPLIFIERS I/O GATING 8 512 x 16 A4 A5 A6 A7 A8 9 99 ROW. ADDRESS BUFFERS(9) 9 ROW DECODER 512 x 512 x 16 MEMORY ARRAY REFRESH COUNTER 512 VBB GENERATOR VCC VSS PIN DESCRIPTIONS PIN NO. 16~19,22~26 14 28 29 13 PIN NAME A0~A8 RAS CASH CASL TYPE Input Input Input Input DESCRIPTION Address Input Row Address : A0~A8 Column Address : A0~A8 Row Address Strobe Column Address Strobe / Upper Byte Control Column Address Strobe / Lower Byte Control WE OE Input Input Input / Output Supply Ground - Write Enable Output Enable Data Input / Output Power, 3.3V Ground No Connect 27 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 I/O0 ~ I/O15 VCC VSS NC Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 2/16 www.DataSheet4U.com EliteMT ABSOLUTE MAXIMUM RATINGS Voltage on Any pin Relative to Vss … ……-0.5V to +4.6V Operating Temperature, TA (ambient) ….0 °C to +70 °C Storage Temperature (plastic) ……….-55 °C to +150 °C Power Dissipation …………………………………0.8W Short Circuit Output Current ……………………50mA M11L416256SA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 °C ≤ TA ≤ 70 °C ; VCC = 3.3V ± 10% unless otherwise noted) PARAMETER CONDITIONS SYMBOL MIN MAX UNITS NOTES Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1.All Voltages referenced to VSS 0V ≤ VIN ≤ VIH(max) 0V ≤ VOUT ≤ VCC Output(s) disable IOH = -2 mA IOL = 2 mA VCC VSS VIH VIL ILI ILO VOH VOL 3.0 0 2.0 -0.3 -10 -10 2.4 - 3.6 0 VCC +0.3 0.8 10 10 0.4 V V V V μA μA 1 1 1 V V PARAMETER CONDITIONS RAS , CAS cycling , tRC =min SYMBOL MAX -35 UNITS NOTES Operating Current ICC1 150 4 2 mA mA mA mA mA mA mA μA 1,2 Standby Current TTL interface , RAS , CAS = VIH , DOUT =High-Z CMOS interface, RAS , CAS ≥ VCC-0.2V ICC2 RAS only refresh Current tRC = min tPC = min RAS =VIH, CAS = VIL ICC3 ICC4 ICC5 ICC6 150 150 5 150 2 1,3 1 EDO Page Mode Current Standby Current CAS Before RAS Refresh Current tRC = min RAS , CAS ≤ 0.2V, DOUT = High-Z, CMOS interface RAS = CAS = VIL, Battery Backup Current (S-ver. only) Self Refresh Current (S-ver. only) ICC7 400 WE = OE = A0~A8 = VCC -0.2 or 0.2V DQ0~DQ15 = VCC -0.2, 0.2V or open ICC8 400 μA Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 3/16 www.DataSheet4U.com EliteMT CAPACITANCE (Ta = 25 °C , VCC = 3.3V ± 10%) PARAMETER SYMBOL TYP MAX M11L416256SA UNIT Input Capacitance (address) Input Capacitance ( RAS , CASH , CASL , WE , OE ) Output capacitance (I/O0~I/O15) CI1 CI2 CI / O - 5 7 10 pF pF pF AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =3.3V ± 10%, VSS = 0V) (note 14) Test Conditions Input timing reference levels : 0.8V, 2.0V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge SYMBOL MIN -35 MAX UNIT NOTES tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tRCS 65 95 14 42 35 10 10 18 20 35 35 10 25 5 30 5 10 5 0 5 8 0 5 30 18 0 17 25 10K 10K 100K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15,18 22 22 4 5,20 13,20 20 RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time 25 24 19 6,23 7,18 19 RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time 8 18 18 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 4/16 www.DataSheet4U.com EliteMT (Continued) PARAMETER Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS SYMBOL MIN M11L416256SA -35 MAX ns ns ns 9,15,19 9 20 10,17,20 17,26 11,15,18 15,25 15 15 15 15,19 12,20 12,20 UNIT NOTES tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCLCH tCOH tWHZ tRASS tRPS tCHS 0 0 3 3 15 8 0 5 30 5 9 7 0 5 30 51 34 26 2.5 10 10 10 4 4 2 2 0 5 3 3 100 65 -50 7 50 8 CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns RAS to WE Delay Time Column Address to WE Delay Time 11 11 11,18 2,3 CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (512 cycles) RAS to CAS Precharge Time CAS Setup Time(CBR REFRESH) CAS Hold Time(CBR REFRESH) OE Hold Time From WE During Read-Mode-Write Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE Precharge Time OE Setup Prior to RAS During Hidden Refresh Cycle Last CAS Going Low to First CAS Returning High Data Output Hold After CAS Returning Low Output Disable Delay From WE Self Refresh RAS Low Pulse width Self Refresh RAS High Precharge Time Self Refresh CAS Hold Time 1,18 1,19 16 ns ns ns 21 μs ns ns 27,28 27,28 27,28 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 5/16 www.DataSheet4U.com EliteMT Notes : M11L416256SA 1. 2. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD ≥ tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the out