Bi-CMOS LSI

www.DataSheet4U.com Ordering number : ENA0691 Bi-CMOS LSI LV5608LP Overview For CCD Charge pump power supply The LV5608LP is charge pump power supply for CCD. Functions • The charge pump boosts the +3.3V input by multiplying with +6, then by -3 to regulate the voltage to the specified level. • The output voltage is +15V, -7.5V necessary for CCD. • Soft start function incorporated, which reduces the inrush current at start of charge pump. • Short-circuit protection function incorporated. • Four types of operating frequency selectable. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max Pd max Topr Tstg with specified substrate *1 Conditions Ratings 3.5 0.8 -20 to +80 -40 to +125 Unit V W °C °C *1 : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board Allowable Operating Ratings at Ta = 25°C, PGND = 0V Parameter Supply voltage Input CLK frequency Input High voltage Input Low voltage Symbol VDD CKIN VINH VINL SEL=H *2 EN pin EN pin Conditions min 3.0 0.1 0.7VDD -0.1 Ratings typ 3.3 max 3.45 8 VDD 0.4 V MHz V V Unit *2 : Note that the charge pump frequency should be adjusted with S0/S1 so that it becomes 2 MHz or less. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 32207 MS PC 20060728-S00004 No.A0691-1/8 www.DataSheet4U.com LV5608LP Electrical Characteristics at Ta = 25°C, VDD = 3.3V, SGND = 0V, PGND = 0V,IH=20mA, IL=5mA, S0=H, S1=L, Unless otherwise specified Parameter Circuit current dissipation Symbol IDD1 IDD2 VH output load current VL output load current Reference voltage IH ave IL ave VREF EN = L EN = H no load VDD = 3.0V VDD = 3.0V VDD = 3.0 to 3.45V, design guarantee Ta = -20°C to +80°C, design guarantee Output voltage accuracy VH VL Output voltage at OFF VH holding time Protection circuit masking time VH load regulation VL load regulation Input pin current VH monitoring voltage Power efficiency Inrush current Oscillation frequency VOFF Toff Tmask ΔVH ΔVL Iin VTvlon Peff Irush f clk 1.5 2 CP+Regulator (VH+VL) Load 1mA → 20mA Load 0.5mA → 8mA Pins EN, S0, S1, SEL and CLK 12.6 After capacitive discharge VLoff → VHoff 1.239 14.55 -7.65 -50 4.5 12 15 -7.5 0 5.6 18 20 10 17.5 10 70 600 2.5 -8 1.305 1.37 15.35 -7.25 50 7.5 32 30 55 22.5 Conditions min Ratings typ 15 17 max 30 25 20 μA mA mA mA V V V V mV ms ms mV mV μA V % mA MHz Unit Note : The design specification items are design guarantees and are not measured. Package Dimensions unit : mm (typ) 3322 1.0 Pd max – Ta Specified circuit board : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board With specified substrate TOP VIEW 3.5 SIDE VIEW BOTTOM VIEW (0.13) (0.125) 13 (C0.116) 12 18 19 Allowable power dissipation, Pd max – W 0.8 3.5 0.6 7 24 6 0.5 1 (0.5) 0.4 0.4 0.36 SIDE VIEW 0.83 0.2 0.15 Independent IC 0.07 (0.035) 0.25 0 – 20 0 20 40 60 80 100 SANYO : VCT24(3.5X3.5)X01 Ambient temperature, Ta – °C No.A0691-2/8 www.DataSheet4U.com LV5608LP Pin Assignment PGND1 20 VL C33 TEST VL C32 C31A 24 S0 S1 EN SGND SVDD CLK 1 2 3 4 5 6 7 23 22 21 19 18 VM C13 17 C12A 16 C11A 15 PVDD 14 C12B 13 PGND 8 9 10 11 12 SEL VH C23 VH C22 C21A NC Top view Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name S0 S1 EN SGND SVDD CLK SEL VH C23 VH C22 C21A NC C11B PGND C12B PVDD C11A C12A VM C13 C31B PGND1 C31A VL C32 VL C33 TEST Boost capacitor connection pin (driver side) +3-fold boost power GND pin Boost capacitor connection pin (driver side) Power system VDD pin Boost capacitor connection pin (load transfer side) Boost capacitor connection pin (load transfer side) Boost voltage output (+3VDD) +2-fold and -1-fold boost capacitor connection pin (driver side) +2-fold and -1-fold boost power GND pin -1-fold boost capacitor connection pin (load transfer side) Boost voltage output (-3VDD) VL (-7.5V) regulator output pin Test pin (OPEN or GND short-circuited) Charge pump frequency changeover pin Charge pump frequency changeover pin System enable pin (Hi active) Small signal system GND pin Small signal system VDD pin External CLK input pin CLK selector pin (L: built-in CLK, H: external CLK) VH (+15V) regulator output pin Boost voltage output (+6VDD) Boost capacitor connection pin (on the load transfer side) Mode C11B C31B No.A0691-3/8 www.DataSheet4U.com LV5608LP Block Diagram 10μF /VDD VDD 3.3V PVDD 14 SVDD 1μF /VDD 4 PGND 20 TSD bandgap voltage reference +3VDD 5 +3 times step up circuit 12 16 17 15 13 PGND C12B C11B 1μF /VDD C11A 1μF /2VDD C12A 2.2μF /3VDD 18 VM C13 PGND1 To A 0.22μF /3VDD C31B 19 21 -1 times step up circuit +2 times step up circuit 1μF /3VDD C21A VH C22 A C31A 10 1μF /3VDD VL C32 22 -3VDD timing generator 2.2μF /6VDD +6VDD 9 VL C33 1μF VL=-7.5V 23 VL Reg sequence generator VH Reg 8 2.2μF VH C23 VH=+15V 2bitMUX EN 3 1 S0 2 S1 2MHz oscillator TEST 24 divider MUX 7 SEL Lo : internal CLK Hi : external CLK 6 CLK No.A0691-4/8 www.DataSheet4U.com LV5608LP Short-circuit Protection VH and VL output pins incorporate the short-circuit protection function. When the output pins are short-circuited to allow the large current to flow, IC is latched OFF to interrupt output. To reset from the interrupted state, set the EN pin to L, then reset it again to H. Frequency Selection The charge pump operating frequency can be changed with S0 and S1 logics. For light load, the reactive load can be reduced by lowering the operating frequency. SEL logic also enables synchronous operation with external CLK. The charge pump is operated with the frequency equivalent to 1/2 of input CLK. (The IC internal oscillator is used for the sequence, so that it is normally ON regardless of SEL. For minimum 9.4ms after startup with the EN signal set to H, the IC internal clock is used to operate the charge pump with 1 MHz regardless of the input of SEL, S0, and S1 pins. After the 9.4ms(min) period, the charge pump frequency is changed over according to the state of SEL, S0, and S1 pins. The changeover frequency is set as shown in the table right. S0 L H L H S1 L L H H CP operating frequency SEL=L 1MHz 500kHz 250kHz 125kHz SEL=H 1/2 CLK 1/4 CLK 1/8 CLK 1/16 CLK SEL L H IC internal oscillator Synchronous operation with external CLK Internal Equivalent Circuit S0 pin S1 pin SEL pin clk clk/2 clk/4 clk/8 4-input multiplexer B Y Internal 1MHz A 2-input multiplexer VH regulator start signal L H in 9.4 ms (min) after EN = H Truth Table SEL Y LA HB D Q Q D Q Q D Q Q Truth Table S0 S1 L L L H L H H H Y clk clk/2 clk/4 clk/8 Y D CLK pin Q Q Charge pump clock External signal input pin Internal signal No.A0691-5/8 www.DataSheet4U.com LV5608LP External clock signal startup sequence Set EN = H by setting V DD at 3 V or more. V Stop at EN = L or over-current protection Never set V DD at 3 V or less till the sequence is over (7.5 ms after EN = L). DD EN Charge pump (C23) Regulator (C22) S0 S1 SEL Frequency selection Frequency selection External clock selected Do not attempt change the signal after 9.4 ms from EN = H. Do not attempt change the signal after 9.4 ms from EN = H. Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection Frequency selection External clock selected Do not attempt change the signal after 9.4 ms from EN = H. Do not attempt change the signal after 9.4 ms from EN = H. Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection Frequency selection External clock selected * Internal 1 MHz SEL=L (Internal clock) * CP clock 1MHz * CP clock 500kHz * CP clock 250kHz * CP clock 125kHz CLK SEL=H (External clock) * CP clock 1/2φ * CP clock 1/4φ * CP clock 1/8φ * CP clock 1/16φ * IC internal signal Internal clock started at 1 MHz 9.4ms(min) Steady operation Internal clock Stop started at 1 MHz sequence 9.4ms(min) 7.5ms(max) Steady operation Stop sequence 7.5ms(max) EN Pin and VDD Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset. To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more. Note that operation with VDD and EN pin short-circuited cannot be made. Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max) passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence logic to operate correctly. No.A0691-6/8 www.DataSheet4U.com LV5608LP Rise/fall Sequence EN IDD mA MAX 0 VREF +6VDD +3VDD Charge pump output -3VDD VH VTvlon REG output VL 5.5ms 2ms 2ms 18.9ms 3.3ms 6.1ms* Toff *The VL startup time at VH ≥ 10V and after elapse of 6.1ms is the reference time for CLK = 2MHz. No.A0691-7/8 www.DataSheet4U.com LV5608LP Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, charact