Pci to Ultra Scsi I/o Processor Technical Manual

www.DataSheet4U.com TECHNICAL MANUAL LSI53C825A/825AE PCI to SCSI I/O Processor Version 3.1 January 2001 ® S14058 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000159-00, Fourth Edition (January 2001) This document describes the LSI Logic LSI53C825A/AE PCI to SCSI I/O Processor and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, visit us at http://www.lsilogic.com. www.DataSheet4U.com LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered trademarks or trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. ii Preface This book is the primary reference and technical manual for the LSI Logic LSI53C825A/825AE PCI to SCSI I/O Processor. It contains a complete functional description for the LSI53C825A/825AE and includes complete physical and electrical specifications for the LSI53C825A/825AE. www.DataSheet4U.com Audience This technical manual is intended for system designers and programmers who are using this device to design a SCSI port for PCI-based personal computers, workstations, or embedded applications. Organization This document has the following chapters and appendixes: • Chapter 1, Introduction, includes general information about the LSI53C825A and other members of the LSI53C8XX family of PCI to SCSI I/O Processors. Chapter 2, Functional Description, describes the main functional areas of the chip in more detail, including the interfaces to the SCSI bus. Chapter 3, Signal Descriptions, describes the chip’s connection to the PCI bus, including the PCI commands and configuration registers supported. Chapter 4, Registers, contains the pin diagrams and definitions of each signal. Chapter 5, SCSI SCRIPTS Instruction Set, describes each bit in the operating registers, organized by address. • • • • Preface iii • • • Chapter 6, Specifications, defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C825A. Appendix A, Register Summary, contains a register summary. Appendix B, External Memory Interface Diagram Examples, contains several example interface drawings to connect the LSI53C825A to an external ROM. Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3 Parallel Interface) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www.lsilogic.com www.DataSheet4U.com iv Preface SCSI SCRIPTS™ Processors Programming Guide, Version 2.2, Order Number S15044.A PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. www.DataSheet4U.com Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision 1.0 2.0 3.0 3.1 Date 6/95 3/96 12/97 1/01 Remarks Revision 1.0 Revision 2.0 Revision 3.0 Product names changed from SYM to LSI. Preface v www.DataSheet4U.com vi Preface Contents Chapter 1 www.DataSheet4U.com Introduction 1.1 General Description 1.2 Package and Feature Options 1.2.1 PCI Pad Power-up Sequence ® Technology 1.3 TolerANT 1.4 LSI53C825A Benefits Summary 1.4.1 SCSI Performance 1.4.2 PCI Performance 1.4.3 Integration 1.4.4 Ease of Use 1.4.5 Flexibility 1.4.6 Reliability 1.4.7 Testability Functional Description 2.1 PCI Addressing 2.1.1 Configuration Space 2.1.2 PCI Bus Commands and Functions Supported 2.1.3 PCI Cache Mode 2.2 SCSI Functional Description 2.2.1 SCSI Core 2.2.2 DMA Core 2.2.3 SCRIPTS Processor 2.2.4 Internal SCRIPTS RAM 2.2.5 SDMS: The Total SCSI Solution 2.2.6 Prefetching SCRIPTS Instructions 2.2.7 Opcode Fetch Burst Capability 2.3 External Memory Interface 2.4 PCI Cache Mode 1-1 1-2 1-3 1-3 1-4 1-4 1-5 1-6 1-6 1-7 1-7 1-8 Chapter 2 2-1 2-1 2-2 2-4 2-10 2-10 2-11 2-11 2-11 2-12 2-13 2-14 2-14 2-17 Contents vii www.DataSheet4U.com 2.5 2.4.1 Load and Store Instructions 2.4.2 3.3 V/5 V PCI Interface 2.4.3 Additional Access to General Purpose Pins 2.4.4 JTAG Boundary Scan Testing 2.4.5 Big and Little Endian Support 2.4.6 Loopback Mode 2.4.7 Parity Options 2.4.8 DMA FIFO 2.4.9 SCSI Bus Interface 2.4.10 Select/Reselect During Selection/Reselection 2.4.11 Synchronous Operation 2.4.12 Achieving Optimal SCSI Send Rates 2.4.13 Interrupt Handling 2.4.14 Chained Block Moves Power Management 2.5.1 Power State D0 2.5.2 Power State D3 2-17 2-17 2-17 2-18 2-19 2-20 2-21 2-23 2-27 2-33 2-33 2-34 2-35 2-42 2-46 2-46 2-46 Chapter 3 Signal Descriptions 3.1 PCI Bus Interface Signals 3.1.1 System Signals 3.1.2 Address and Data Signals 3.1.3 Interface Control Signals 3.1.4 Arbitration Signals 3.1.5 Error Reporting Signals 3.1.6 SCSI Bus Interface Signals 3.1.7 Additional Interface Signals 3.1.8 External Memory Interface Signals 3.1.9 JTAG Signals 3.2 MAD Bus Programming Registers 4.1 Configuration Registers 4.2 Operating Registers 3-6 3-6 3-7 3-8 3-9 3-9 3-10 3-11 3-14 3-15 3-15 Chapter 4 4-1 4-18 viii Contents Chapter 5 www.DataSheet4U.com SCSI SCRIPTS Instruction Set 5.1 Low Level Register Interface Mode 5.2 High Level SCSI SCRIPTS Mode 5.2.1 Sample Operation 5.3 Block Move Instructions 5.3.1 First Dword 5.3.2 Second Dword 5.4 I/O Instruction 5.4.1 First Dword 5.4.2 Second Dword 5.5 Read/Write Instructions 5.5.1 First Dword 5.5.2 Second Dword 5.5.3 Read-Modify-Write Cycles 5.5.4 Move To/From SFBR Cycles 5.6 Transfer Control Instructions 5.6.1 First Dword 5.6.2 Second Dword 5.7 Memory Move Instructions 5.7.1 First Dword 5.7.2 Read/Write System Memory from SCRIPTS 5.7.3 Second Dword 5.7.4 Third Dword 5.8 Load and Store Instructions 5.8.1 First Dword 5.8.2 Second Dword Specifications 6.1 DC Characteristics 6.2 TolerANT Technology Electrical Characteristics 6.3 AC Characteristics 6.4 PCI and External Memory Interface Timing Diagrams 6.4.1 Target Timing 6.4.2 Initiator Timing 6.4.3 External Memory Timing 5-1 5-2 5-3 5-6 5-6 5-13 5-14 5-14 5-23 5-24 5-24 5-26 5-26 5-27 5-29 5-29 5-36 5-36 5-37 5-38 5-38 5-38 5-40 5-41 5-42 Chapter 6 6-1 6-7 6-11 6-13 6-15 6-24 6-32 Contents ix 6.5 6.6 6.7 Appendix A Appendix B PCI and External Memory Interface Timing SCSI Timing Diagrams Package Drawings 6-44 6-45 6-52 Register Summary External Memory Interface Diagram Examples Index Customer Feedback www.DataSheet4U.com Figures 1.1 1.2 2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 3.3 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6.1 6.2 6.3 6.4 6.5 LSI53C825A External Memory Interface LSI53C825A Chip Block Diagram DMA FIFO Sections LSI53C825A Host Interface Data Paths LSI53C825A Differential Wiring Diagram Regulated Termination Determining the Synchronous Transfer Rate Block Move and Chained Block Move Instructions LSI53C825A Pin Diagram LSI53C825AJ Pin Diagram LSI53C825A Functional Signal Grouping SCRIPTS Overview Block Move Instruction Register I/O Instruction Register Read/Write Instruction Register Transfer Control Instruction Memory Move Instruction Load and Store Instruction Format Rise and Fall Time Test Conditions SCSI Input Filtering Hysteresis of SCSI Receivers Input Current as a Function of Input Voltage Output Current as a Function of Output Voltage 1-9 1-10 2-23 2-27 2-31 2-32 2-35 2-45 3-2 3-3 3-5 5-5 5-8 5-17 5-25 5-31 5-39 5-43 6-9 6-9 6-9 6-10 6-10 x Contents www.DataSheet4U.com 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 B.1 External Clock Reset Input Interrupt Output PCI Configuration Register Read PCI Configuration Register Write Operating Register/SCRIPTS RAM Read Operating Register/SCRIPTS RAM Write External Memory Read External Memory Write Nonburst Opcode Fetch Burst Opcode Fetch Back-to-Back Read Back-to-Back Write Burst Read Burst Write Read Cycle, Normal/Fast Memory (≥ 64 Kbytes), Single Byte Access Write Cycle, Normal/Fast Memory (≥ 64 Kbytes), Single Byte Access Read Cycle, Normal/Fast Memory (≥ 64 Kbytes), Multiple Byte Access Write Cycle, Normal/Fast Memory (≥ 64 Kbytes), Multiple Byte Access Read Cycle, Slow Memory (≥ 64 Kbytes) Write Cycle, Slow Memory (≥ 64 Kby