Description
PRELIMINARY PRODUCT SPECIFICATIONS ® Integrated Circuits Group 16M Flash and 2M SRAM (Model No.: LRS1329) Stacked Chip LRS1329 Spec No.: MFM2-J11601 Issue Date: June 10, 1999 SHARP l LRS1329 Handle this document carefully for it contains material protected by international full or in part,. of this material is prohibited copyright law. Any reproduction, without the express written permission of the company. When using the products covered herein, please observe.the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics * Instrumentation and measuring *Machine tools -Audiovisual equipment *Home appliances * Communication equipment other equipment l than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating redundancy, and other appropriate measures into the design fail-sale operation, for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, transportation equipment * Mainframe computers -Traffic control systems . Gas leak detectors and automatic cutoff devices *Rescue and security equipment . Other safety devices and safety equipment,etc. automobiles, and other (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, . accuracy. * Aerospace equipment . Communications equipment for trunk lines *Control equipment for the nuclear power industry -Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding above three Paragraphs to a sales representative the interpretation of the company. herein to a sales of the or l Please direct representative all queries regarding of the company. the products covered SHARP LRS1329 1 Contents 1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5. Command Definitions for Flash Memory - * - - * - * - - - - - * - - - - 5 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . f . . . . . 8 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . 8 10. pi* Capacitance . - . . . . . a . . . . . a . - . a s s s s s ‘- s - e 8 11. DC Electrical Characteristics - * - * - * * * + * - * - - * - * - * 9 12. AC Electrical Characteristics (Flash Memory) - * - * * - * * - * - * - 11 13. AC Electrical Characteristic’s (SRAM) - - * - * - - - - - - * - - - * - 18 14. Data Retention 15. Notes Characteristics for SRM * - * - * - - - * - - - * - - - 21 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17. Design Consideration . . . . . . . . . . . . , . . . . . . . . . . . . 24 SHARI= LRS1329 2 Part 1 Overview 1. Description The LR S 1 3 2 9 is a combination memory organized as lMx16/2M flash memory and 256K x8 bit static RAM in one package. Features OPower ONot supply designed 72 pin or rated CSP as radiation hardened ) plastic package P-type bulk silicon. and SRAM has . . . . . . . . 2.7 v -25 to 3.6 V +85 ‘c ~8 bit OOperat ing temperature “c to 0 ( LCSPO72-P-0811 P-type bulk silicon, OFlash Flash memory has Memory Time current (Ihe current Read Word/Byte Block erase (The current Architecture Parameter Blocks/ Boot Location for F-V,, pin) for write F-V, . . . . 100 ns (Max.) OAccess OOperating pin) . . . - 25 mA (Max. t,U=200ns) . . . . 17 mA (Max.) . . . - 17 mA (Max.) * * * * 10 PA (Max. F-ZZF-Vcc-0. F-EsO. ZV, F-V&O. 2V, 2V) ODeep power down current OOptimized Array Blocking Two 4X-word/8K-byte Boot Blocks/ Six 4K-word/8K-byte Thirty-one 32X-word/64K-byte Main Blocks/ Top 0 Extended Cycling Capabi 1 i ty Erase Cycles Suspend to Read write ~100,000 Block Word/Byte write 0 Enhanced Automated Suspend Options Block Erase Suspend to Nerd/Byte Block Erase Suspend to Read SRAM OAccess OOperat OStandby OData Time ing current current current . . . . . . . . . . . . . . . . . . . . . 85 ns 30 d 3 &ax. > OhL > s) mA (Max. t,, t,=lp 15 PA (Max.) 15 ,uA (Max.) retention SHARP LRS1329 2. Pin Configuration r INDEX 3 Block erase and Word/Byte Write : Vi, or V w, Read 1 V,, or V k,, Deep Power Down: VIL F7@ Write Protect (Flash) Two Boot Blocks Locked : ViL (With F-&V m,Erase/Write can operate to all block) F-BYTE Byte Enable (Flash); x8 mode: VIL, x16 mode: VI, Ready/Busy (Flash) F-RY/BY During an Erase or Write operation: V,, Block Erase and Word/Byte Write Suspend: High-Z Deep Power Down: V, DQ,to DQ, Data Input/Outputs (Common) F-DQ 8 to F-DQ is Data Inputs/Outputs (Flash) ; Not used in x8 mode. Power Supply (Flash) F-V,, Power Supply (SRAl4) s-“cc Write, Erase Power Supply (Flash) F-V,, Block Erase and Word/Byte Write : F-V,,=V,,, : Al 1 Blocks Locked 1 F-V,,<Vppll( F-GND GND (Flash) GND (SRAM) S-GND No Connect NC r T, to T, Test pins (Should be open) SHARI= 3. Truth Table (*l) Flash Read output Disable Write Read output Disable Write Read Power Output Disable Write Standby Reset Down tes) *l. ’ Power Standby *6 x L ’ Standby *2,3,4 *6 *6 *6 *6 *6 *6 *6 H H XLXXLH H H SRAM Note *4.5 L H F-a F-B LRS1329 4 F-3 L F-E H S-CE, S-GE, S-s S* *7 H L x F-DQ F-mtoDPh , to hu& H DOUT L DOUT 1 High-Z Bigh-Z x.7-. H L DIN DIN High-Z DOUT High-Z DIN DOUT High-Z L H ’ ’ L H H L L H X H L x x x x x X Standby Reset Down High-Z DIN Bigh-2 *7 High-Z L=V,,, H=V,, , X=H or L . Refer to DC Characteristics. *2. Command writes involving block erase or word/byte write are reliably executed when F-V,,+., and F-V,=2.7V to 3-W. Block erase or word/byte write with V,,<F-B<V, produce spurious results and should not be attempted. *3. Refer Section 5. Flash Memory Comand Definition for valid DIN during a write operation. *4. Never hold F-2 low and F-s low at the same timing. *5. F-A., set to V,, or VI, in byte mode (F-BYTE=Vn). -1 *6. F-‘RP set to V,, or V,, . *7. See the following SRAM Standby mode. Block Diagram F-V, F-V, F-GND ----------------, . .F-?i? i =- > F-RY/?% 16M(x8/x16) b i t Flash memory F-D’& to F-W,, F-X F-E F-m F* F-BYTE :’ + :> :T +DQ, S-A,, S-E, s-c> S-OE S-IRE 4 b I > j > ; > 2M (x8) bit SRAM to W, s-v, S-GND SHARP I 5 Command Definitions LRS1329 for Flash Memory (*I) 5 I Word/Byte Write Block Write Block Write Note) *l. Erase and Word/Byte Suspend Erase and Word/Byte Resume 2 1 1 *5 *5 *5 Wr i t,e Write Write WA XA XA 4OH or 10H Boll DOH Write WA WD Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. ’ *2. BUS operations are defined in 3. Truth Table. *3. XA=Any valid address within the device. IA=Identifier Code Address. BA=Address within the block being erased. WA=Address of memory location to be written. SRD=Data read from status register(See the next page”Status Register Definition”). WD=Data to be written at location WA. Data is latched on the rising edge of F-%?or F-5 (whichever goes high first). II&Data read from identifier codes. *4. See the Following Identifier Codes. *5. See the following Write Protection Alternatives. Write Operation Block Erase or Word/Byte Write F-V,, VIL >V,, F-i@ X V “t v IH VIH F?@ X X X VIL VIH Protection Alternatives Effect All Blocks Locked. All Blocks Locked. All Blocks Unlocked. 2 Boot Blocks Locked. All Blocks Unlocks. SHARP 6. Status WSMS Register ESS 6 Definition ES 5 LRS1329 6 WBWS 4 VPPS 3 NOTES: WBWSS 2 DPS 1 R 0 7 S R. 7= WRITE STATE MACHINE STATUS( W SMS) 1 = Ready 0 = Busy SR. 6= ERASE SUSPEND STATUS( ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed Check RYm or SR.7 to determine block erase OI word/byte write completion. SR.6-0 are invalid whi 1e SR. 7=“0”. SR.5=ERASESTATUS( ES ) 1 = Error in Block Erasure 0 = Successful Block Erase S R. 4= WORD/BYTE WRITE STATUS ( WBWS 1 = Error in Word/Byte Write 0 = Successful Word/Byte Write SR. 3= V,, STATUS ( VPPS ) 1 = F-V,, Low Detect, Operation 0 = F-V,, OK ) If both SR. 5 and SR.4 are “1”s after a block erase attempt, an improper command sequence was entered. Abort SR.3 does not provide a continuous of F-V,, level. The WSM interrogates indication and S R. 2 = WORD/BYTE WRITE SUSPENDED STATUS (WBWSS) 1 =Word/ByteWrite 0 =Word/ByteWrite Suspended in Progress/Completed indicates the F-V,, level only after Block Erase or Word/ByteWrite command sequences. SR.: is not guaranteed to reports accurate feedback on 1y when F-V, +Vepm,2. S R . l= DEVICE PROTECT STATUS ( D P S ) 1 = F-‘WP or F-@’ Lock Detected, Operation Abort 0 = Unlock S R. 0 = RESERVEDFOR FUTURE ENBANCEMENTS 4,R > The WSM interrogates the F-s and F-E only after Block Erase orWord/ByteWrite command sequences. It informs the system, depending on the attempted operation, if the F-w is not VIM, F-E is not Vm+ SR.0 is reserved for future use and should masked out when polling the status register. be SHARP Memory Map for Flash Memory Address [A,.-hl LRS1329 7 4K*word/8K-byte 4K-word/BK-byte 4K-word/BK-byte 32K-word/64K-byte 32X-word/64K-byte 323.word/64K-byte 32K-word/64K-byte 32K-word/64K.byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-aord/64K-byte 32K-word/64K-byte 32K-word/64K-byte

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LRS1805A

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