Emulated Peak Current Mode Buck Controller

www.DataSheet4U.com LM3495 Emulated Peak Current Mode Buck Controller for Low Output Voltage April 2006 LM3495 Emulated Peak Current Mode Buck Controller for Low Output Voltage General Description The LM3495 is a PWM buck regulator which implements a unique emulated peak current mode control. This control method eliminates the switching noise which typically limits current mode operation at extremely short duty cycles and high operating frequency. The switching frequency is programmable between 200 kHz and 1.5 MHz, and can also be synchronized to an external clock. The LM3495 is also very fault tolerant with both switch node short, hiccup mode, and adaptive duty cycle limit protection. A 0.6V 1% reference and glitch free pre-biased start-up ensure the most demanding digital loads operate reliably. Internal soft start and the ability to track the output of another supply make the LM3495 versatile and efficient. Features n n n n n n n n n n n n n n Input voltage from 2.9V to 18V Output voltage adjustable from 0.6V to 5.5V Feedback Accuracy: ± 1% Low-side Sensing, Programmable Current Limit without sense resistor Input Under Voltage Lockout Hiccup mode current limit protection eliminates thermal runaway during fault conditions Internal soft start with tracking capability 200 kHz to 1.5 MHz Switching frequency, Synchronizable On-chip gate drivers Soft output discharge during shutdown Startup into output pre-bias Operation from a single input rail Adaptive Duty Cycle Limit TSSOP-16 package Applications n Wide input voltage buck converters with low voltage, high accuracy outputs n Core logic regulators n High-efficiency buck regulation Typical Application 20169901 © 2006 National Semiconductor Corporation DS201699 www.national.com LM3495 Connection Diagram TOP VIEW 20169902 16-Lead Plastic TSSOP θJA = 155˚C/W Ordering Information Part Number LM3495MTC LM3495MTCX NSC Package Drawing MTC16 MTC16 Supplied As 92 Units Per Rail 2.5k Units Per Reel TRACK (Pin 9): Tracking pin. To force the output of the LM3495 to track another power supply, connect a resistor divider (smaller than 10 kΩ for better precision) from the output of the other supply directly to this pin. When not used, this pin should be connected directly to the VLIN5 pin. FB (Pin 10): Feedback pin. Connecting a resistor divider from the output voltage to this pin sets the DC level of the output voltage. COMP/SD (Pin 11): Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop. This pin must be left floating for the converter to regulate the output voltage in steady state. Forcing this pin below 0.3V shuts down the regulator. SGND (Pin 12): Signal ground. Ground connection for the low power analog circuitry. Connect this pin to the PGND pin with a separate trace. VIN (Pin 13): Input voltage. Input to an internal 4.7V linear regulator. Bypass this pin with a minimum 1 µF ceramic capacitor. VLIN5 (Pin 14): Output of the internal 4.7V linear regulator. Provides power to the high-side bootstrap and low-side driver. Bypass this pin with a 2.2 µF ceramic capacitor to PGND. LG (Pin 15): Gate drive for the low-side N-channel FET. This signal is interlocked with HG to avoid shoot-through. PGND (Pin 16): Ground connection for the power circuitry. Connect to the source of the low-side FET and the output capacitor with heavy traces or a copper plane. Pin Descriptions BOOST (Pin 1): Supply rail for the high-side FET gate drive. The voltage should be at least one gate threshold above the regulator input voltage to properly turn on the high-side FET. HG (Pin 2): Gate drive for the high-side N-channel FET. This signal is interlocked with LG to avoid shoot-through. SW/CSH (Pin 3): Return path for the high-side FET driver and top Kelvin sense point for the load current. Connect this pin as close as possible to the drain of the low-side FET with a separate trace. Also used along with CSL for zero crossing detection. CSL (Pin 4): Bottom sense point for the load current. Connect this as close as possible to the source of the low-side FET with a separate trace. ILIM (Pin 5): Current limit threshold setting. This pin sources a fixed 20 µA current. A resistor of appropriate value should be connected between this pin and the drain of the low-side FET. FPWM (Pin 6): Control mode select. An open circuit at this pin allows the IC to operate in skip mode at light loads. A logic low or connection to ground forces PWM operation at all times. This pin should not be pulled up to any voltage above 3.0V. SNS (Pin 7): Output voltage sense pin. Connect this pin as close as possible to the positive terminal of the output capacitor with a separate trace. This pin connects to an internal FET that discharges the output capacitor during shutdown. FREQ/SYNC (Pin 8): Switching frequency select pin and input for external clock. Connect a resistor from this pin to ground to determine switching frequency. Alternatively, a logic level clock signal between 200 kHz and 1.5 MHz can be applied to this pin through a 100 pF DC blocking capacitor to set the switching frequency. www.national.com 2 LM3495 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN, ILIM SW/CSH (Note 5) BOOST, HG BOOST to SW FB TRACK, FREQ, FPWM, VLIN5, SNS, LG, CSL Storage Temperature −0.3V to 20V −0.5V to 20V −0.3V to 25V −0.3V to 6V −0.3V to 2V −0.3V to 6V −65˚C to +150˚C Soldering Information Lead Temperature (soldering, 10 sec) Infrared or Convection (15 sec) ESD Rating (Note 2) 260˚C 235˚C 2kV Operating Ratings (Note 1) Supply Voltage Range (VIN) BOOST to SW Junction Temperature 2.9V to 18V 2.5V to 5.5V −40˚C to +125˚C Electrical Characteristics Specifications with standard type are for TJ = 25˚C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V. Typ (Note 4) 0.6 0.6 0.1 0.1 2.55 2.26 2.6 2.3 1.8 2.7 2.45 Symbol SYSTEM PARAMETERS VFB ∆VFB/VFB VON IQ Parameter Conditions -20˚C to 85˚C -40˚C to 125˚C 2.9V < VIN < 18V, COMP/SD = 1.5V 1.1V < COMP/SD < 1.8V VIN Rising VIN Falling COMP/SD > 0.3V Not switching COMP/SD < 0.3V Shutdown, VIN = 18V Min 0.594 0.591 Max 0.606 0.609 Units FB Pin Voltage Line Regulation Load Regulation UVLO Thresholds Operating VIN Current V % % V mA Quiescent Current IILIM VILIM-MAX ISD VHICCUP tDELAY tCOOL tSS VOVP IFPWM VFPWM-LO RSNS ILIM Pin Source Current Maximum Current Limit Sense Voltage COMP/SD Pin Pull-up current COMP/SD Pin Hiccup Threshold Hiccup Delay Cool Down Time Until Restart Internal Soft start Time Over Voltage Protection Threshold FPWM Pin Pull-up Current FPWM Operation Threshold SNS Pin Input Resistance 33 18 20 200 22 µA µA mV 2.6 µA V Cycles Cycles Cycles 132 % µA V kΩ COMP/SD = 0V 2 2 16 4096 400 As a % of nominal output voltage FPWM = 0V FPWM Voltage Falling SNS = 1.5V COMP/SD > 0.3V SNS = 1.5V COMP/SD = 0V BOOST - SW = 5.5V BOOST - SW = 4.5V BOOST - SW = 4.5V 116 125 4.5 0.9 30 RDIS GATE DRIVE IBOOST RDS1 RDS2 SNS Pin Discharge FET RDSON 350 440 530 Ω BOOST Pin Leakage Current High-Side FET Driver Pull-up ON resistance High-Side FET Driver Pull-down ON resistance 25 4.5 0.9 nA Ω Ω 3 www.national.com LM3495 Electrical Characteristics Specifications with standard type are for TJ = 25˚C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V. (Continued) Typ (Note 4) 1.4 0.7 Symbol RDS3 RDS4 OSCILLATOR fSW Parameter Low-Side FET Driver Pull-up ON resistance Low-Side FET Driver Pull-down ON resistance PWM Frequency VLIN5 = 5.5V VLIN5 = 5.5V Conditions Min Max Units Ω Ω RADJ = 150 kΩ RADJ = 54.9 kΩ RADJ = 17.8 kΩ 450 200 500 1500 1.2 0.3 125 550 kHz VSYNC-HI VSYNC-LO tON-SKIP Threshold for SYNC on FREQ Pin Threshold for SYNC on FREQ Pin On Time During Skip Mode SYNC Voltage Rising SYNC Voltage Falling VO = 1.5V fSW = 500 kHz VO = 1.5V fSW = 500 kHz V V ns tON-MAX tOFF-MIN ERROR AMP gM BW-3dB IFB ISOURCE ISINK VCOMP-HI VCOMP-LO TRACKING VTEND VTRACK-OS Adaptive Maximum On-time Limit Minimum Off-time Transconductance Open Loop Bandwidth FB Pin Bias Current COMP/SD Pin Source Current COMP/SD Pin Sink Current COMP/SD Pin Voltage High Clamp COMP/SD Pin Voltage Low Clamp Track End Threshold Track to FB Offset 750 300 750 ns ns µmho MHz nA µA µA V V V mV V V 0.4 V V COMP/SD Floating VFB = 0.6V VFB = 0.5V, COMP/SD = 1.5V VFB = 0.7V, COMP/SD = 1.5V VFB = 0.5V VFB = 0.7V 5 1 40 40 2 0.9 0.6 TRACK = 0.55V VIN = 12V, VLIN5 Current = 25 mA VIN = 3.3V, VLIN5 Current = 25 mA COMP/SD Pin Voltage Rising COMP/SD Pin Voltage Falling 0.2 15 4.72 3.0 0.3 0.26 INTERNAL VOLTAGE REGULATOR VVLIN5 Voltage at VLIN5 Pin (Note 3) LOGIC INPUTS AND OUTPUTS VSD-HI VSD-LO COMP/SD Pin Logic High Trip Point COMP/SD Pin Logic Low Trip Point Junction-to-Ambient Thermal Resistance Thermal Shutdown Threshold Thermal Shutdown Hysteresis THERMAL CHARACTERISTICS θJA TSD TSD-HYS 155 150 15 ˚C/W ˚C ˚C Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Elec