Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer

LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer ADVANCE INFORMATION June 2004 LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer General Description The LM2501 device is a Serializer/Deserializer that adapts existing video busses to Mobile Pixel Link (MPL). MPL is intended to replace wide LVCMOS video interfaces inside portable electronics equipment benefiting their cost, size, EMI and power consumption. By using the LM2501 SERDES chipset, the interconnect is reduced from 12 active signals to only 3 active signals providing a 75% reduction. This eases interconect and flex design, size and cost. Contained in a 24 lead Ultra Thin CSP Package, the Serializer resides beside the video source (camera) and translates the parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable to the Deserializer located by the respective destination Video Input Port. An extra clock transport is provided to deliver a clock signal to the target. For example, from the main board to the flip board where the camera module is located. Transmission of the clock also benefits from MPL’s low power transmission and low EMI. The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD, MC and WC signals are powered down to save current and reduce power dissipation. Features n n n n n 160 Mbps Raw Throughput MPL-0 Meets MPL Physical Layer Specification Configurable as a Serializer or Deserializer Complete LVCMOS to MPL Translation Serializes 8-bit Camera Interface — 8-bit color data — plus VSYNC and HSYNC bits Link power down mode reduces quiescent power under ∼ 10 µA (actual TBD) 1.7V–3.1V and 2.9-3.1V Supply Voltage Interfaces to 1.8V–3.0V Logic Offered in a small 24L UCSP Package — 3.5 mm X 4.5 mm — 0.6 mm Max Height n n n n System Benefits n n n n n Reduced Wire Interface Low Power Low EMI Extra Clock Transport Intrinsic Level Translation Typical Application Diagram 20091601 Ordering Information NSID LM2501SL Package Type 24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm Package ID SLE24A I2C ® is a registered trademark of Phillips Corporation. © 2004 National Semiconductor Corporation DS200916 www.national.com LM2501 Connection Diagram 20091612 TOP VIEW General Block Diagrams: Serializer and Deserializer 20091613 www.national.com 2 LM2501 Pin Description Pin Name No. of Pins 1 1 1 2 I/O, Type Description MPL SERIAL BUS PINS MD MC MG Mode[1:0] IO, MPL IO, MPL Ground I, LVCMOS MPL Data line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. MPL Clock line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. See VSSA below. Mode Configuration Input pins: Mode[1:0], NOTE - Applies to REV F/G Samples only. 00 : Deserializer 01 : Serializer with PD* input 10 : Reserved 11 : Reserved Power_Down. Input pin. Active Low. When PD* is Low the device is in the sleep state. 8-bit Bi-directional Data Bus – Serializer Input, Deserializer Output VSYNC – Serializer Input, Deserializer Output HSYNC – Serializer Input, Deserializer Output Pixel Clock. Serializer Input, Deserializer Output Extra Clock Input for WhisperClock Link – Deserializer Input. Serializer Output. Extra WhisperClock MPL signal – Serializer is an MPL input signal, Deserializer is an MPL output signal. Power Supply Pin for the MPL Interface. 3.0V ± 3% Ground Pin for the MPL Interface, also known as MG (MPL Ground) Power Supply Pin for the digital core and Serializer PLL. 3.0V ± 3% Ground Pin for the digital core and Serializer PLL. Power Supply Pin for the parallel interface. 1.7V to 3.1V Ground Pin for the parallel interface. CONFIGURATION/PARALLEL BUS PINS PD* D0–D7 VS HS PCLK WHISPER CLOCK WCLKIO WC 1 8 1 1 1 1 1 I, LVCMOS IO, LVCMOS IO, LVCMOS IO, LVCMOS IO, LVCMOS IO, LVCMOS IO, MPL POWER/GROUND PINS VDDA VSSA VDD VSS VDDIO VSSIO 1 1 1 1 1 1 Power Ground Power Ground Power Ground Notes: I = Input, O = Output, IO = Input/Output Do NOT float unused inputs. ES Revision notes Rev D/E Rev F Rev G Sampled on MPL200EVK S/D* and TM pins changed to Mode[1:0] MPL RX enhancements Use prior datasheet edition Use this datasheet edition 3 www.national.com LM2501 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDDA) Supply Voltage (VDD) Supply Voltage (VDDIO) LVCMOS Input/Output Voltage MPL Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 Seconds ESD Ratings: HBM, 1.5 kΩ, 100pF ≥ ± 2 kV −0.3V to +TBDV −0.3V to +TBDV −0.3V to +TBDV −0.3V to (VDDIO +0.3V) TBD +150˚C −65˚C to +150˚C +260˚C EIAJ, 0Ω, 200 pF 24L UCSP Package Derate TBD Package above 25˚C ≥ ± 200V TBD W TBD mW/˚C Maximum Package Power Dissipation Capacity at 25˚C Recommended Operating Conditions Min Typ Max Supply Voltage VDDA to VSSA and VDD to VSS VDDIO to VSSIO PLK Clock Frequency WC Clock Frequency Ambient Temperature 2.9 1.7 4 4 0 25 3.0 3.1 3.1 16 28 70 V V MHz MHz ˚C Units Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol MPL IOLL IOMS IOHL IB VIH VIL IIN IIH IIL VOH VOL IOS Logic Low Current Mid Scale Current Logic High Current Current Bias Input Voltage High Level Input Voltage Low Level Input Current (includes IOZ) Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Output Short Circuit Current Total Supply Current — Enabled IOH = −2 mA IOL = 2 mA VOUT = 0V TBD 0.8 IB 4.8 IB 5.0 IB 3.0 IB 1.0 IB 150 VDDIO +0.3 0.3 VDDIO 0 0 0 +5 +1 +1 0.2 VDDIO 1.2 IB 5.3 IB µA µA µA µA Parameter Conditions Min Typ Max Units LVCMOS (1.7V to 3.1V) 0.7 VDDIO −0.3 −5 −1 −1 0.8 VDDIO V V µA µA µA V V mA SUPPLY CURRENT ICC PCLK = 16MHz WC = 28MHz MD = 0101-1010 pattern CL = 15 pF Serializer TBD Deserializer TBD 1 1 TBD 10 10 µA µA µA TBD µA ICCZ Supply Current — Disable Power_Down Mode PD* = L PD* = L www.national.com 4 LM2501 Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol tSET tHOLD tRISE tFALL PCLOW PCHIGH tDVBC tDVAC tDVBC tDVAC POWER UP TIMING (see Figures 5, 6) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 tPAZ tPZA WC Start Up Delay WC Low Initialization Low State WC Pulse Width High WC Low State WCIN to WCOUT Latency (SER) TBD SER PLL Lock Time MC Low Initialization Low State MC Pulse Width High MC Low State SER Latency DES Latency Disable Time to Power Off Enable Time from Power Off Figure 6 11 11 11 Figure 5 Planned Rev G ES test Chip will double WC cyc counts on T1 to T4 (SER) parameters to support higher WC rates. 100 11 11 11 6 12 12 12 7 9 4,096 12 12 12 TBD TBD 13 13 13 13 13 13 8 WCCYC WCCYC WCCYC WCCYC WCCYC WCCYC MCCYC MCCYC MCCYC MCCYC MCCYC MCCYC µs µs Parameter Set Time - Data to Clock Hold Time - Clock to Data Rise Time Fall Time PCLK Low PCLK High Data Valid before Clock Data Valid after Clock Figure 1 Figure 2 TBD TBD Outputs, CL = 15 pF 50 50 Inputs Conditions Figure 2 Min TBD TBD Typ Max Units ns ns ns ns % % ns ns PARALLEL BUS TIMING SERIAL BUS TIMING POWER OFF TIMING 5 www.national.com LM2501 Input Timing Requirements Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol fWC WCDC tT Parameter Clock Frequency Clock Duty Cycle Clock Transition Times (Rise or Fall, 10%–90%) Clock Frequency Clock Period Clock Duty Cycle Clock transition Time Conditions Min 4 45 1 50 Typ Max 28 55 6 Units MHz % ns REFERENCE CLOCK (WCLKIN) PIXEL CLOCK (PCLK) fPCLK tCP CLKDC tT 4 62.5 45 1 50 16 250 55 6 MHz ns % ns Note 1: “Absolute Maximum Ratings“ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VDD = VDDA = 3.0V and VDDIO = 2.7V and TA = 25˚C. Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified. Timing Diagrams 20091610 FIGURE 1. Serial Data Valid 20091611 FIGURE 2. Parallel Set, Hold and Data Valid www.national.com 6 LM2501 Application Information Typical application connections for the LM2501 are shown below. 20091614 FIGURE 3. Camera Application The application shown in Figure 3 illustrates a connection between an Image sensor and a host utilizing an MPL-0 link. . 7 www.national.com LM2501 Functional Description SERIAL BUS OPERATION Bus Overview The MPL bus is a simple 2-signal line interface that is intended to replace wide low voltage CMOS video busses inside handheld portable devices. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termina- tion is provided internal to the MPL receiver. The MPL interface is designed to be used with common 50 Ω lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 0.3 meters. This device is meets the requirements of the MPL-0 Standard (PHY Layer only). SERIAL BUS TIMING Data valid is relative to both edges as shown in Figure 4. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, (Note relative to both edges). 20091602 FIGURE 4. Master-to-Slave Timing (MC, MDm) SERIAL BUS PHASES There are three bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines. Two