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LM2240 Programmable Timer Counter
August 1990
LM2240 Programmable Timer Counter
General Description
The LM2240 Programmable Timer Counter is a monolithic controller capable of both monostable and astable operation Monostable operation allows accurate microsecond to five day time delays Long delays up to three years can easily be generated by cascading two timers The timer consists of a time-base oscillator programmable 8-bit counter and control flip-flop An external resistor-capacitor (RC) network sets the oscillator frequency and allows delay times from 1 RC to 255 RC to be selected In the astable mode of operation a single RC network sets the base frequency The frequencies of the squarewaves at the 8 outputs are each at different factors of 2 from the base frequency If 2 or more of the outputs are shorted together various pulse patterns can be generated These frequencies or pulse patterns can also easily be synchronized to an external signal The trigger reset and outputs are all TTL and CMOS compatible for easy interface with digital systems The timer’s high accuracy and versatility in producing a wide range of time delays makes it ideal as a direct replacement for mechanical or electromechanical devices
Features
Y Y Y Y Y Y Y Y
Accurate timing from microseconds to days Programmable delays from 1 RC to 255 RC TTL and CMOS compatible outputs Timing directly proportional to RC time constant High accuracy External sync and modulation capability Wide supply voltage range Excellent supply voltage rejection
Connection Diagram
16-Lead Molded DIP
TL H 10837 – 1
Top View See NS Package Number N16E Order Number LM2240N
C1995 National Semiconductor Corporation
TL H 10837
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature Range Molded DIP Lead Temperature Molded DIP (Soldering 10 Sec ) Power Dissipation (Note 2) Junction Temperature
b 65 C to a 150 C
Supply Voltage Output Current Output Voltage Regulator Output Current ESD Tolerance (Note 3)
18V 10 mA 18V 5 0 mA 2000V
265 C 1 8W 150 C
Operating Ratings
Temperature Range Supply Range (Note 4) 0 C to 70 C 4V to 15V
LM2240 Electrical Characteristics
TA e a 25 C VCC e a 5 0V R e 10 kX C e 0 1 mF unless otherwise specified See Block Diagram Symbol Characteristic Conditions Min Typ Max Units
GENERAL CHARACTERISTIC ICC Supply Current Total Circuit VCC e 5 0V VTR e 0V VRS e 5 0V VCC e 15V VTR e 0V VRS e 5 0V Counter Only VREG Regulator Output Measured at Pin 15 VCC e 5 0V VCC e 15V TIME-BASE tACC Dt DT Timing Accuracy (Note 5) Timing Shift with Temperature Timing Shift with Supply Max Frequency Modulation Voltage Level VRS e 0 VTR e 5 0V 0 C s TJ s 70 C VCC e 5 0V VCC e 15V VCC t 8 0V R e 1 0 kX C e 0 007 mF Measured at Pin 12 VCC e 5 0V VCC e 15V RT CT Recommended Range of Timing Resistor Recommended Range of Timing Capacitor (Note 6) 0 001 0 01 2 80 35 200 80 0 08 130 3 50 10 5 10 1000 MX mF 4 20 03 % V kHz V 50 % ppm C 39 58 40 13 15 44 63 68 V 70 18 mA
Dt DV fMAX VMOD
Note 1 Absolute maximum ratings indicate limits beyond which damage to the component may occur Note 2 Rating applies to ambient temperature at 25 C Above this temperature derate at 15 mW C Note 3 Human body model C e 100 pF RS e 1500X Note 4 For operation below 4 5 VDC short pin 15 to pin 16 Note 5 Timing error solely introduced by LM2240 measured as % of ideal time-base period of T e RC Note 6 Under the conditions of high supply voltages (VCC l 7 0V) and low values of timing capacitor (CT k 0 1 mF) a 600 pF capacitor may need to be connected from pin 14 to ground to ensure proper operation
2
Electrical Characteristics
TA e a 25 C VCC e a 5 0V R e 10 kX C e 0 1 mF unless otherwise specified See Block Diagram Symbol Characteristic Conditions Min Typ Max Units
TRIGGER RESET CONTROLS VTR ITR ZT tRSPT VRS IR ZR tRSPT COUNTER TRMAX ZI VTH tr tf IOb ICEX Max Toggle Rate Input Impedance Input Threshold Output Rise Time Output Fall Time Sink Current Leakage Current Measured at Pins 1 through 8 RL e 3 0 kX CL e 10 pF VOL s 0 4V VOH e 15V 20 10 Measured at Pin 14 VRS e 0V VTR e 5 0V 15 20 14 180 180 40 0 01 15 mA mA MHz kX V ns Trigger Threshold Trigger Current Trigger Impedance Trigger Response Time (Note 7) Reset Threshold Reset Current Reset Impedance Reset Response Time (Note 7) Measured at Pin 10 VTR e 0V VTR e 0V VRS e 2 0V Measured at Pin 11 VRS e 0V VRS e 0V VTR e 2 0V 14 10 25 10 14 10 25 08 20 20 V mA kX ms V mA kX ms
Note 7 Propagation delay from application of trigger or reset input to corresponding state change in counter output at Pin 1
Block Diagram
TL H 10837 – 2
3
Typical Performance Characteristics
Supply Current vs Supply Voltage in Reset Condition Recommended Range of Timing Component Values (Note 7) Time-Base Period vs External RC
Minimum Trigger and Reset Pulse Widths vs Trigger and Reset Amplitude
Time-Base Period Drift vs Supply Voltage
Minimum Trigger Retrigger Timing vs Timing Capacitor
Normalized Change in Time-Base Period vs Modulation Voltage
Time-Base Period vs Temperature
Time-Base Period vs Temperature
TL H 10837 – 3
4
Functional Description
(Figure 3) The circuit starts timing when a trigger is applied and automatically resets itself to complete the timing cycle when a programmed count is completed Each of the various multiplies of T shown at the LM2240’s outputs in Figure 3 represent the duration of time after a trigger pulse that that particular output is low (it’s not the period of the waveform) if the output is not tied to any other outputs TO represents the duration of time that the circuit output which is the common point of all the counter outputs which are shorted together is low If none of the counter outputs are connected back to the reset terminal (switch S1 open) the circuit operates in an astable or free running mode following a trigger input
TL H 10837 – 4
VCC e Pin 16 GND e Pin 9
FIGURE 1 Logic Symbol When power is applied to the LM2240 with no trigger or reset inputs activated the circuit starts with all outputs HIGH Application of a positive going trigger pulse to the trigger pin initiates the timing cycle The trigger input activates the time-base oscillator enables the counter section and sets the counter outputs LOW The time-base oscillator generates timing pulses with a period T e 1 RC this is the period of the waveform appearing at pin 14 These clock pulses are counted by the binary counter section The timing sequence is completed when a positive going reset pulse is applied to the Reset pin Once triggered the circuit is immune from additional trigger inputs until the timing cycle is completed or a reset input is applied If both the reset and trigger are activated simultaneously the trigger takes precedence
Figure 2 gives the timing sequence of output waveforms at various circuit terminals subsequent to a trigger input When the circuit is in a reset state both the time-base and the counter sections are disabled and all the counter outputs are HIGH
TL H 10837 – 6
FIGURE 3 Basic Circuit Connection for Timing Applications (Monostable S1 Closed Astable S1 Open)
Important Operating Information
Ground connection is pin 9 Reset (R) (pin 10) sets all outputs HIGH Trigger (TRIG) (pin 11) sets all outputs LOW Time-base output (TBO) (pin 14) can be disabled by bringing the RC input (pin 13) LOW via a 1 0 kX resistor Normal TBO (pin 14) is a negative going pulse greater than 500 ns
NOTE Under the conditions of high supply voltages (VCC l 7 0V) and low values of timing capacitor (CT k 0 1 mF) the pulse width of TBO may be too narrow to trigger the counter section This can be corrected by connecting a 600 pF capacitor from TBO (pin 14) to ground (pin 9)
TL H 10837 – 5
FIGURE 2 Timing Diagram of Output Waveforms In monostable applications one or more of the counter outputs are connected to the reset terminal with S1 closed
Reset (pin 10) stops the time-base oscillator Outputs (O0 VOL s 0 4V O128) (pins 1 – 8) sink 2 0 mA current with
For use with external clock minimum clock pulse amplitude should be 3 0V with greater than 1 0 ms pulse duration
5
Circuit Controls
Counter Outputs (O0 O128 Pins1 thru 8) The binary counter outputs are buffered open collector type stages as shown in the block diagram Each output is capable of sinking 2 0 mA at 0 4V VOL In the reset condition all the counter outputs are HIGH or in the nonconducting state Following a trigger input the outputs change state in accordance with the timing diagram of Figure 2 The counter outputs can be used individually or can be connected together in a wired-OR configuration as described in the programming segment of this datasheet Reset and Trigger Inputs (R and TRIG Pins 10 and 11) The circuit is reset or triggered with positive-going control pulses applied to pins 10 and 11 respectively The threshold level for these controls is approximately two diode drops ( 1 4V) above ground Minimum pulse widths for reset and trigger inputs are shown in the Performance Curves Once triggered the circuit is immune to additional trigger inputs until the end of the timing cycle Modulation and Sync Input (MOD Pin 12) The oscillator time-base period (T) can be modulated by applying a DC voltage to MOD pin 12 (see Performance Curves) Also the time-base oscillator can be synchronized to an external clock by applying a sync pulse to MOD pin 12 as shown in Figure 4 Recommended sync pulse widths and amplitudes are also given
TL H 10837 – 8
FIGURE 5 Typical Pull-in Range for Harmonic Synchronization Time-Base Output (TBO Pin 14) The time-base output is an open-collector type stage as shown in the block diagram and requires a 20 kX pull-up resistor to pin 15 for proper circuit operation In the reset state the time-base output is HIGH After triggering it produces a negativ
