(LFEC Series) LatticeECP/EC Family Data Sheet

www.DataSheet4U.com LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features ■ Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported − − − − − − LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL SSTL 3/2 Class I, II, SSTL18 Class I HSTL 18 Class I, II, III, HSTL15 Class I, III PCI LVDS, Bus-LVDS, LVPECL, RSDS ■ sysDSP™ Block (LatticeECP™ Versions) • High performance multiply and accumulate • 4 to 10 blocks − 4 to 10 36x36 multipliers or – 16 to 40 18x18 multipliers or − 32 to 80 9x9 multipliers ■ Dedicated DDR Memory Support • Implements interface up to DDR400 (200MHz) ■ sysCLOCK™ PLLs • Up to 4 analog PLLs per device • Clock multiply, divide and phase shifting ■ Embedded and Distributed Memory • 18 Kbits to 645 Kbits sysMEM™ Embedded Block RAM (EBR) • Up to 163 Kbits distributed RAM • Flexible memory resources: − Distributed and block memory ■ System Level Support • IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability • SPI boot flash interface • 1.2V power supply ■ Low Cost FPGA • Features optimized for mainstream applications • Low cost TQFP and PQFP packaging ■ Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces: Table 1-1. LatticeECP/EC Family Selection Guide Device PFU/PFF Rows PFU/PFF Columns PFUs/PFFs LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sysDSP Blocks 1 LFEC1 12 16 192 1.5 6 18 2 — — 1.2 2 67 97 112 LFEC3 16 24 384 3.1 12 55 6 — — 1.2 2 67 97 145 160 LFEC6/ LFECP6 24 32 768 6.1 25 92 10 4 16 1.2 2 LFEC10/ LFEC15/ LFEC20/ LFEC33/ LFEC40/ LFECP10 LFECP15 LFECP20 LFECP33 LFECP40 32 40 1280 10.2 41 277 30 5 20 1.2 4 40 48 1920 15.4 61 350 38 6 24 1.2 4 44 56 2464 19.7 79 424 46 7 28 1.2 4 64 64 4096 32.8 131 535 58 8 32 1.2 4 64 80 5120 41.0 164 645 70 10 40 1.2 4 18x18 Multipliers1 VCC Voltage (V) Number of PLLs Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 144-pin TQFP (20 x 20 mm) 208-pin PQFP (28 x 28 mm) 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 672-ball fpBGA (27 x 27 mm) 900-ball fpBGA (31 x 31 mm) 1. LatticeECP devices only. 97 147 195 224 147 195 288 195 352 360 400 360 496 496 576 © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 Introduction_01.2 Lattice Semiconductor Introduction LatticeECP/EC Family Data Sheet Introduction The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions. The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os. Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prevalent in cost-sensitive applications. The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeECP/EC Family Data Sheet Architecture November 2004 Preliminary Data Sheet Architecture Overview The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks as shown in Figure 2-2. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the outside rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every three rows of PFF blocks there is a row of PFU blocks. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM or ROM. The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeECP/EC architecture provides up to four PLLs per device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™ port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core voltage. © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 Architecture_01.3 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet Figure 2-1. Simplified Block Diagram, LatticeECP/EC Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (PFU without RAM) sysCLOCK PLL Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (Fast PFU without RAM/ROM) sysDSP Block sysCLOCK PLL Programmable Functional Unit (PFU) 2-2 Lattice Semiconductor Architecture LatticeECP/EC Family Data Sheet PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-3. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 Slice 1 Slice 2 Slice 3 D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. 2-3 Lattice Semiconductor Figure 2-4. Slice Diagram To / From Different slice / PFU Architecture LatticeECP/EC Family Data Sheet Slice OFX1 A1 B1 C1 D1 CO F1 F SUM D LUT4 & CARRY CI Q1 FF/ Latch To Routing From Routing M1 M0 LUT Expansion Mux OFX0 A0 B0 CO C0 D0 LUT4 & CARRY C