Digital Audio Interface Receiver

www.DataSheet4U.com Ordering number : ENN7457 CMOS LSI LC89052T Digital Audio Interface Receiver 1. Overview The LC89052T is an audio LSI that demodulates according to the data format for the data transferred between digital audio devices via the IEC 60958/61937 and EIAJ CP-1201. It supports sampling frequencies of up to 192kHz and output data lengths up to 28 bits. Despite it is compact and made in a low cost, the LC89052T includes a built-in oscillator and serial data input circuits and allows the system microcontroller to read the sub-code Q data and channel status. It supports low-power modes that allow low-voltage operation. It also supports a lower power mode, which is suitable for application that requires long battery life, such as cell phones, PDAs, and portable audio devices. 3. Package Dimensions unit: mm 3260A [ LC89052T ] 6.5 24 13 4.4 6.4 1 (0.5) 0.08 (1.0) 2. Features • Incorporates a built-in PLL circuit to synchronize with transferred bi-phase mark signal. • Can receive input with sampling frequencies of 32kHz to 192kHz. • Can set the upper limit of sampling frequency of received data. • Can receive input data of specific sampling frequencies. • Outputs the following clocks: fs, 64fs, 128fs, 256fs, 384fs, and 512fs. • Contains a built-in oscillation amplifier that can construct a oscillation circuit. An external clock can be also provided. • Outputs an externally input clock signal that can be used as the A/D converter clock when the PLL is unlocked. • Maintains the continuity of the output clock when the clock is switched. • Equipped with a serial digital audio data input pin that can be configured for a demodulated signal output. • Can output up to 28 bits of data, and also supports output of I2S and input NRZ data. • Can output bi-phase mark signal synchronized with the 128fs bit clock. • Provides an output pin for the channel status bit 1 non-PCM data detection bit. • Provides an output pin for the channel status emphasis detection bit. • Supports a lower-power mode. Continued on next page. 1.2max 0.5 12 0.22 0.15 SANYO:TSSOP24(225mil) 71003 SI IM No.7457-1/42 0.5 www.DataSheet4U.com LC89052T Continued from preceding page. • Calculates the input signal sampling frequency and outputs it from the microcontroller interface. • Can output the first 48 bits of the channel status with the microcontroller interface. • Can output the 80-bit sub-code Q data with CRC flags via microcontroller interface. • Outputs various state changes as interrupt signals to the microcontroller interface. • Equipped with a user definable output port that can be selected from the following functions. —Microcontroller interface register output (for power saving mode optical module control signals, etc.) —Signal output of transitional period where VCO clock and external input clock are switched. • Can dispense with un-used microcontroller control. • 3.3V single source power supply (Can operate at a minimum voltage of 2.7V.) • The TTL input ports can support 5V interface operation. • Package: TSSOP-24 4. Pin Assignments XOUT 1 ERROR 2 PD 3 NC 4 CE 5 CL 6 DI 7 DO 8 E / INT 9 AUDIO 10 UGPI 11 RXIN 12 Top view 24 XIN 23 SDIN 22 DATAO 21 LRCK 20 BCK 19 CKOUT 18 DGND 17 AGND 16 NC 15 LPF 14 AV DD 13 DV DD LC89052T No.7457-2/42 www.DataSheet4U.com LC89052T 5. Pin Description Table 5.1 Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name XOUT ERROR ___ PD NC CE CL DI DO E / INT ______ AUDIO _____ UGPI RXIN DVDD AVDD LPF NC AGND DGND CKOUT BCK LRCK DATAO SDIN XIN O O O O I5 I O I5 I5 I5 O O O O I5 I/O O O I5 Oscillation amplifier circuit output pin PLL lock error and data error output pin System reset and low-power mode control input pin Non connection Microcontroller interface: chip enable input pin Microcontroller interface: serial clock input pin Microcontroller interface: write data input pin Microcontroller interface: read data output pin Pre-emphasis detection or microcontroller interface interrupt output pin Channel status bit 1 non-PCM data detection output pin User settable output pin Digital data input pin Digital power supply pin Analog power supply pin PLL loop filter pin Non connection Analog GND pin Digital GND pin System clock output pin 64fs clock output pin Fs clock output pin Function * ** *** Demodulated data output pin Serial digital data input pin Oscillator or external clock input pin * ** *** : Microcontroller register output or clock switching transition period signal. : 128fs, 256fs, 384fs, 512fs, or oscillator amplifier outputs. : Other than I2S mode ; Low: right channel, High: left channel. I2S mode ; Low: left channel, High: right channel. 1) I/O voltage handling : I or O pins : –0.3 to +3.6V, I5 pins : –0.3 to +5.5V 2) To prevent logic circuit latch-up, all power supply must be applied or removed simultaneously. No.7457-3/42 www.DataSheet4U.com LC89052T 6. Block Diagram DI 7 CL 6 CE 5 PD 3 AUDIO 10 DO E/INT 8 9 Microcontroller I/F Fs calu. UGPI 11 Demodulation & RXIN 12 Lock detection C&U 2 Data buffer ERROR LPF 15 PLL Clock selector Audio I/F 19 CKOUT 20 BCK 21 LRCK 22 DATAO XIN 24 XOUT 1 Amp. 23 SDIN No.7457-4/42 www.DataSheet4U.com LC89052T 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7.1 Absolute Maximum Ratings at AGND = DGND = 0V Parameter Maximum supply voltage Maximum supply voltage Input voltage 1 Input voltage 2 Output voltage Storage temperature Operating temperature Maximum output current Symbol AVDD max DVDD max VIN1 VIN2 VOUT Tstg Topg Ii, IOUT 7-1-6 7-1-1 7-1-2 7-1-3 7-1-4 7-1-5 Conditions Ratings –0.3 to 4.6 –0.3 to 4.6 –0.3 to 3.9 –0.3 to 5.8 –0.3 to 3.9 –55 to 125 –30 to 70 ±20 unit V V V V V °C °C mA 7-1-1 : 7-1-2 : 7-1-3 : 7-1-4 : 7-1-5 : 7-1-6 : AVDD pin. DVDD pin. XIN pin. _____ RXIN, SDIN, PD, CE, CL, and DI pins. ______ _____ XOUT, ERROR, DO, E/INT, AUDIO, UGPI, CKOUT, BCK, LRCK, and DATAO pins. Per single input or output pin. 7.2 Recommended Operating Conditions Table 7.2 Recommended Operating Conditions Parameter Supply voltage 1 Supply voltage 2 Input voltage range 1 Input voltage range 2 Operating temperature Symbol AVDD, DVDD AVDD, DVDD VIN1 VIN2 Vopg Conditions 7-2-1 7-2-2 7-2-3 7-2-4 min 2.7 3.0 0 0 –30 typ 3.3 3.3 3.3 3.3 max 3.6 3.6 3.6 5.5 70 unit V V V V °C 7-2-1 : 7-2-2 : 7-2-3 : 7-2-4 : PLLCK [1:0] = "00" or PLLCK [1:0] = "01" PLLCK [1:0] = "10" or PLLCK [1:0] = "11" XIN pin _____ RXIN, SDIN, PD, CE, CL, and DI pins 7.3 Input and Output Pin Capacitances Table 7.3 Input and Output Pin Capacitances Parameter Input pins Output pins CIN COUT Symbol Conditions 7-3-1 7-3-1 min typ max 10 10 unit pF pF 7-3-1 : AVDD = DVDD = VIN1 = VIN2 = 0 V, Ta = 25°C, f = 1MHz No.7457-5/42 www.DataSheet4U.com LC89052T 7.4 DC Characteristics Table 7.4 DC Characteristics at Ta = -30 to 70°C, AVDD = DVDD = 3.0 to 3.6V, AGND = DGND = 0V Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Power consumption Power consumption Power consumption Power consumption Symbol VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL IDD1 IDD2 IDD3 IDD4 7-4-6 7-4-7 7-4-8 7-4-9 4.5 5 6.5 7-4-5 DVDD – 0.8 0.4 13 0.1 9 10 7-4-4 DVDD – 0.8 0.4 7-4-3 7-4-2 2.0 –0.3 DVDD – 0.8 0.4 Conditions 7-4-1 min 0.7DVDD 0.2DVDD 5.8 0.8 typ max unit V V V V V V V V V V mA µA mA mA 7-4-1 : 7-4-2 : 7-4-3 : 7-4-4 : 7-4-5 : 7-4-6 : 7-4-7 : 7-4-8 : 7-4-9 : CMOS level pins: XIN pin. TTL level pins: Input pins other than those listed above. IOH = –8mA, IOL = 6mA: CKOUT pin. IOH = –2mA, IOL = 2mA: BCK, LRCK, DATAO, and DO pins. IOH = –1mA, IOL = 1mA: Output pins other than those listed above. Operating mode: PLLSEL = "0", AMPOPR = "0", fs = 44.1kHz, CL = 30pF ___ Low power mode condition 1) : PD = low Low power mode condition 2) : PDOWN [1:0] = "01", XIN = 11.2896MHz, CL = 30pF Low power mode condition 3) : PDOWN [1:0] = "10", XIN = 11.2896MHz, CL = 30pF No.7457-6/42 www.DataSheet4U.com LC89052T 7.5 AC Characteristics Table 7.5 AC Characteristics at Ta = -30 to 70°C, AVDD = DVDD = 3.0 to 3.6V, AGND = DGND = 0V Parameter RXIN sampling frequency RXIN sampling frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency CKOUT clock frequency CKOUT clock jitter CKOUT to BCK delay BCK to DATAO delay ____ UGPI low-level pulse width Symbol fFS1 fFS2 fXF1 fXF2 fXF3 fXF4 fXF5 fXF6 fMCK tj tMBO tBDO tCKT 7-5-9 Conditions 7-5-1 7-5-2 7-5-3 7-5-4 7-5-5 7-5-6 7-5-7 7-5-8 2 200 10 5 100 min 30 30 11.2896 12.2880 16.9344 22.5792 24.5760 33.8688 100 typ max 195 108 unit kHz kHz MHz MHz MHz MHz MHz MHz MHz ps ns ns ms 7-5-1 : 7-5-2 : 7-5-3 : 7-5-4 : 7-5-5 : 7-5-6 : 7-5-7 : 7-5-8 : 7-5-9 : PLLCK [1:0] = "00" Settings other than PLLCK [1:0] = "00". XISEL [3:0] = "0000" XISEL [3:0] = "0001" XISEL [3:0] = "0010" XISEL [3:0] = "0100" XISEL [3:0] = "0101" XISEL [3:0] = "0110" When signal output is set during a transitional period of clock switching. tCKT UGPI CKOUT tMBO BCK tBDO DATAO LRCK Figure 7.1 AC Characteristics No.7457-7/42 www.DataSheet4U.com LC89052T 7.6 Microcontroller Interface AC Characteristics Table 7.6 Microcontroller Interface AC Characteristics at Ta = -30 to 70°C, AVDD = DVDD = 3.0 to 3.6V, AGND = DGND = 0V Parameter ___ PD low-level pulse width E/INT high-level pulse width CL low-level pulse width CL high-level pulse width CL to CE setup time CL to CE hold time CL to DI setup time CL to DI hold time CL to CE hold time CL to DO delay time CE to DO delay time Symbol tPDdw tINTuw tCLdw tCLuw tCEsetup tCEhold tDIsetup tDIhold tCLhold tCLtoDO tCEtoDO 7-6-1 Conditions min 200 5 100 100 50 50 50 50 50 20 20 1/fs 63 typ max unit µs µs ns ns ns ns ns n