Interrupt Controller

KS32C50100 RISC MICROCONTROLLER INTERRUPT CONTROLLER 13 • • • INTERRUPT CONTROLLER The KS32C50100 interrupt controller has a total of 21 interrupt sources. Interrupt requests can be generated by internal function blocks and at external pins. The ARM7TDMI core recongnizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt request (FIQ). Therefore all KS32C50100 interrupts can be categorized as either IRQ or FIQ. The KS32C50100 interrupt controller has an interrupt pending bit for each interrupt source. Four special registers are used to control interrupt generation and handling: Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to 20. Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source. Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the interrupt pending status is maintained until the CPU clears it by writing a "1" to the appropriate pending register. When the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". The service routine must clear the pending condition by writing a "1" to the appropriate pending bit. This avoids the possibility of continuous interrupt requests from the same interrupt pending bit. Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding mask bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global mask bit (bit 21) is set to "1", no interrupts are serviced. However, the source's pending bit is set if the interrupt is generated. When the global mask bit has been set to "0", the interrupt is serviced. • w w w .D t a S a e h t e U 4 .c m o w w w .D at Sh a et e 4U . om c 13-1 INTERRUPT CONTROLLER KS32C50100 RISC MICROCONTROLLER INTERRUPT SOURCES The 21 interrupt sources in the KS32C50100 interrupt structure are listed, in brief, as follows: Table 13-1 KS32C50100 Interrupt Sources Index Values [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] I2C-bus interrupt Ethernet controller MAC Rx interrupt Ethernet controller MAC Tx interrupt Ethernet controller BDMA Rx interrupt Ethernet controller BDMA Tx interrupt HDLC channel B Rx interrupt HDLC channel B Tx interrupt HDLC channel A Rx interrup HDLC channel A Tx interrupt Timer 1 interrupt Timer 0 interrupt GDMA channel 1 interrupt GDMA channel 0 interrupt UART1 receive & error interrupt UART1 transmit interrupt UART0 receive & error interrupt UART0 transmit interrupt External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 Interrupt Source 13-2 KS32C50100 RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS INTERRUPT MODE REGISTER Bit settings in the interrupt mode register, INTMOD, specify if an interrupt is to be serviced as a fast interrupt (FIQ) or a normal interrupt (IRQ). Table 13-2 INTMOD Register Register INTMOD Offset Address 0x4000 R/W R/W Description Interrupt mode register Reset Value 0x00000000 31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTMOD X X X X X X X X X X X X X X X X X X X X X [20:0] Interrupt mode bits NOTE: Each of the 21 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM7TDMI core in FIQ (fast interrupt) mode. Otherwise, it is processed in IRQ mode (normal interrupt). The 21 interrupt sources are mapped as follows: [20] I 2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx i nterrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive & error interrupt [6] UART1 transmit interrupt [5] UART0 receive & error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 Figure 13-1 Interrupt Mode Register (INTMOD) 13-3 INTERRUPT CONTROLLER KS32C50100 RISC MICROCONTROLLER INTERRUPT PENDING REGISTER The interrupt pending register, INTPND, contains interrupt pending bits for each interrupt source. This register has to be cleared at the top of a interrupt service routine. Table 13-3 INTPND Register Register INTPND Offset Address 0x4004 R/W R/W Description Interrupt pending register Reset Value 0x00000000 31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTPND X X X X X X X X X X X X X X X X X X X X X [20:0] Interrupt pending bits NOTE: Each of the 21 bits in the interrupt pending register, INTPND, corresponds to an interrupt source. When an interrupt request is generated, its pending bit is set to 1. The service routine must then clear the pending condition by writing a 1 to the appropriate pending bit at start. The 21 interrupt sources are mapped as follows: [20] I 2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC Tx interrupt [17] Ethernet controller BDMA Rx inter rupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive & error interrupt [6] UART1 transmit interrupt [5] UART0 receive & error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 Figure 13-2 Interrupt Pending Register (INTPND) 13-4 KS32C50100 RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT MASK REGISTER The interrupt mask register, INTMSK, contains interrupt mask bits for each interrupt source. Table 13-4 INTMSK Register Register INTMSK Offset Address 0x4008 R/W R/W Description Interrupt mask register Reset Value 0x003FFFFF 31 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTMSK G X X X X X X X X X X X X X X X X X X X X X [20:0] Individual interrupt mask bits NOTE: Each of the 21 bits in the interrupt mask register, INTMSK, (except for the global mask bit, G) corresponds to an interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the CPU when the corresponding interrupt request is generated. If the mask bit is 0, the interrupt is serviced upon request. And if global mask bit (bit 21) is 1, no interrupts are serviced. (However, the source pending bit is set whenever the interrupt is generated.) After the global mask bit is cleared, the interrupt is serviced. The 21 interrupt sources are mapped as follows: [20] I 2C interrupt [19] Ethernet controller MAC Rx interrupt [18] Ethernet controller MAC T x interrupt [17] Ethernet controller BDMA Rx interrupt [16] Ethernet controller BDMA Tx interrupt [15] HDLC channel B Rx interrupt [14] HDLC channel B Tx interrupt [13] HDLC channel A Rx interrupt [12] HDLC channel A Tx interrupt [11] Timer 1 interrupt [10] Timer 0 interrupt [9] GDMA channel 1 interrupt [8] GDMA channel 0 interrupt [7] UART1 receive & error interrupt [6] UART1 transmit interrupt [5] UART0 receive & error interrupt [4] UART0 transmit interrupt [3] External interrupt 3 [2] External interrupt 2 [1] External interrupt 1 [0] External interrupt 0 [21] Global interrupt mask bit 0 = Enable interrupt requests 1 = Disable all interrupt requests Figure 13-3 Interrupt Mask Register (INTMSK) 13-5 INTERRUPT CONTROLLER KS32C50100 RISC MICROCONTROLLER INTERRUPT PRIORITY REGISTERS The interrupt priority registers, INTPRI0–INTPRI5, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. Each INTPRIn register value determines the priority of the corresponding interrupt source. The lowest priority value is priority 0, and the highest priority value is priority 20. The index value of each interrupt source is written to one of the above 21 positions (see Figure 13-4). The position value then becomes the written interrupt's priority value. The index value of each interrupt source is listed in Table 13-1. Table 13-5 Interrupt Priority Register Overview Registers INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 Offset Address 0x400C 0x4010 0x4014 0x4018 0x401C 0x4020 R/W R/W R/W R/W R/W R/W R/W Description Interrupt priority register 0 Interrupt priority register 1 Interrupt priority register 2 Interrupt priority register 3 Interrupt priority register 4 Interrupt priority register 5 Reset Value 0x03020100 0x07060504 0x0B0A0908 0x0F0E0D0C 0x13121110 0x00000014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTPRI0 INTPRI1 INTPRI2 INTPRI3 INTPRI4 INTPRI5 0 0 0 0 0 0 PRIORITY3 PRIORITY7 0 0 0 0 0 0 PRIORITY2 PRIORITY6 0 0 0 0 0 0 0 0 0 PRIORITY1 PRIORITY5 PRIORITY9 0 0 0 0 0 0 0 0 0 PRIORITY0 PRIORITY4 PRIORITY8 LOW PRIORITY 0 0 0 PRIORITY11 0 0 0 PRIORITY15 0 0 0 PRIORITY19 0 0 0 PRIORITY10 0 0 0 PRIORITY14 0 0 0 PRIORITY18 0 0 0 PRIORITY13 0 0 0 PRIORITY17 0 0 0 PRIORITY12 0 0 0 PRIORITY16 HIGH PRIORITY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIORITY20 HIGH PRIORITY LOW PRIORITY Figure 13-4 Interrupt Priority Registers (INTPRIn) 13-6 KS32C50100 RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT OFFSET REGISTER The interrupt offset register, INTOFFSET, contains the interrupt offset address of the interrupt which has the highest priority among the pending